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ZHCSBM4B September 2013 – August 2015 ISO7142CC

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBQ|16
- MSOI004H

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
	Supply voltage⁽²⁾	V_CC1, V_CC2	–0.5	6	V
	Voltage	INx, OUTx, ENx	–0.5	V_CC + 0.5⁽³⁾	V
I_O	Output current		–15	15	mA
T_J	Maximum junction temperature			150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage		2.7		5.5	V
I_OH	High-level output current	V_CC ≥ 3 V	–4			mA
I_OH	High-level output current	V_CC < 3 V	–2			mA
I_OL	Low-level output current				4	mA
V_IH	High-level input voltage		2		5.5	V
V_IL	Low-level input voltage		0		0.8	V
t_ui	Input pulse duration	V_CC ≥ 4.5 V	20			ns
t_ui	Input pulse duration	V_CC < 4.5 V	25			ns
1 / t_ui	Signaling rate	V_CC ≥ 4.5 V	0		50	Mbps
1 / t_ui	Signaling rate	V_CC < 4.5 V	0		40	Mbps
T_J	Junction temperature				136	°C
T_A	Ambient temperature		–55	25	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO7142CC	UNIT
		DBQ (SSOP)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	104.5	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	57.8	°C/W
R_θJB	Junction-to-board thermal resistance	46.8	°C/W
ψ_JT	Junction-to-top characterization parameter	18.3	°C/W
ψ_JB	Junction-to-board characterization parameter	46.4	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 8	V_CCO ⁽¹⁾ – 0.5			V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 8	V_CCO – 0.1			V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 8			0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 8			0.1	V
V_I(HYS)	Input threshold voltage hysteresis			480		mV
I_IH	High-level input current	V_IH = V_CCI⁽¹⁾ at INx or ENx			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 11	25	70		kV/μs

(1) V_CCI= Supply voltage for the input channel; V_CCO = Supply voltage for the output channel

6.6 Supply Current Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)

	TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
Supply current for V_CC1 and V_CC2	Disable	EN1 = EN2 = 0 V	I_CC1, I_CC2	0.8	1.6	mA
	DC to 1 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1 , I_CC2	3.3	5
	10 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	4.9	7
	25 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	7.3	10
	50 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	11.1	14.5

6.7 Electrical Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 8	V_CCO ⁽¹⁾ – 0.5			V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 8	V_CCO – 0.1			V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 8			0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 8			0.1	V
V_I(HYS)	Input threshold voltage hysteresis			460		mV
I_IH	High-level input current	V_IH = V_CCI⁽¹⁾ at INx or ENx			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 11	25	50		kV/μs

(1) V_CCI= Supply voltage for the input channel; V_CCO = Supply voltage for the output channel

6.8 Supply Current Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)

	TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
Supply current for V_CC1 and V_CC2	Disable	EN1 = EN2 = 0 V	I_CC1, I_CC2	0.5	1	mA
	DC to 1 Mbps	DC signal: V_I = V_CCI or 0 V AC signal: All channels switching with square-wave clock input; C_L = 15 pF	I_CC1, I_CC2	2.5	4
	10 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	3.5	5
	25 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	5	7
	40 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	6.5	10

6.9 Electrical Characteristics—2.7-V Supply

V_CC1 and V_CC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –2 mA; see Figure 8	V_CCO ⁽¹⁾ – 0.3			V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 8	V_CCO – 0.1			V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 8			0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 8			0.1	V
V_I(HYS)	Input threshold voltage hysteresis			360		mV
I_IH	High-level input current	V_IH = V_CCI⁽¹⁾ at INx or ENx			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V; see Figure 11	25	45		kV/μs

(1) V_CCI= Supply voltage for the input channel; V_CCO = Supply voltage for the output channel

6.10 Supply Current Characteristics—2.7-V Supply

V_CC1 and V_CC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)

	TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
Supply current for V_CC1 and V_CC2	Disable	EN1 = EN2 = 0 V	I_CC1, I_CC2	0.4	0.8	mA
	DC to 1 Mbps	DC signal: V_I = V_CCI or 0 V AC signal: All channels switching with square-wave clock input; C_L = 15 pF	I_CC1, I_CC2	2.2	3.5
	10 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	3	4.2
	25 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	4.2	5.5
	40 Mbps	DC signal: V_I = V_CCI or 0 V, AC signal: All channels switching with square wave clock input; C_L = 15 pF	I_CC1, I_CC2	5.4	7.5

6.11 Power Dissipation Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
P_D	Device power dissipation	V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF Input a 25-MHz, 50% duty cycle square wave			170	mW

6.12 Switching Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 8	15	21	38	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 8			3.5	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Same-direction channels			1.5	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Opposite-direction channels			6.5	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time				14	ns
t_r	Output signal rise time	See Figure 8		2.5		ns
t_f	Output signal fall time	See Figure 8		2.1		ns
t_PHZ, t_PLZ	Disable propagation delay, high/low-to-high impedance output	See Figure 9		7	12	ns
t_PZH	Enable propagation delay, high impedance-to-high output	See Figure 9		6	12	ns
t_PZL	Enable propagation delay, high impedance-to-low output	See Figure 9		12	23	us
t_fs	Fail-safe output delay time from input data or power loss	See Figure 10		8		μs
t_GR	Input glitch rejection time			9.5		ns

(1) Also known as pulse skew

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads.

6.13 Switching Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 8	16	25	46	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 8			3	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Same-direction Channels			2	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Opposite-direction Channels			6.5	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time				21	ns
t_r	Output signal rise time	See Figure 8		3		ns
t_f	Output signal fall time	See Figure 8		2.5		ns
t_PHZ, t_PLZ	Disable propagation delay, from high/low to high-impedance output	See Figure 9		9	14	ns
t_PZH	Enable propagation delay, from high-impedance to high output	See Figure 9		9	17	ns
t_PZL	Enable propagation delay, from high-impedance to low output	See Figure 9		12	24	us
t_fs	Fail-safe output delay time from input data or power loss	See Figure 10		7		μs
t_GR	Input glitch rejection time			11		ns

(1) Also known as pulse skew

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.14 Switching Characteristics—2.7-V Supply

V_CC1 and V_CC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 8	18	28	50	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 8			3	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Same-direction Channels			3	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Opposite-direction Channels			8.5	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time				24	ns
t_r	Output signal rise time	See Figure 8		3.5		ns
t_f	Output signal fall time	See Figure 8		2.8		ns
t_PHZ, t_PLZ	Disable propagation delay, from high/low to high-impedance output	See Figure 9		10	15	ns
t_PZH	Enable propagation delay, from high-impedance to high output	See Figure 9		10	19	ns
t_PZL	Enable propagation delay, from high-impedance to low output	See Figure 9		12	23	us
t_fs	Fail-safe output delay time from input data or power loss	See Figure 10		7		μs
t_GR	Input glitch rejection time			12		ns

(1) Also known as pulse skew

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.15 Typical Characteristics

Figure 1. ISO7142 Supply Current for All Channels vs Data Rate

Figure 2. High-Level Output Voltage
vs High-Level Output Current

Figure 3. Low-Level Output Voltage
vs Low-Level Output Current

Figure 5. Propagation Delay Time
vs Free-Air Temperature

Figure 7. Peak-Peak Output Jitter vs Data Rate

Figure 4. V_CC Undervoltage Threshold
vs Free-Air Temperature

Figure 6. Input Glitch Rejection Time
vs Free-Air Temperature