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ZHCSDA4C November 2012 – January 2015 DS90UH927Q-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTA|40
- MPQF134A

散熱焊盤機械數據 (封裝 | 引腳)

RTA|40
- QFND447B

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾⁽³⁾

	MIN	MAX	UNIT
Supply Voltage – V_DD33⁽⁴⁾	−0.3	4.0	V
Supply Voltage – V_DDIO⁽⁴⁾	−0.3	4.0	V
LVCMOS I/O Voltage	−0.3	(V_DDIO + 0.3)	V
Serializer Output Voltage	−0.3	2.75	V
Junction Temperature		150	°C
Storage Temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering specifications, see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(4) The DS90UH927Q-Q1 V_DD33 and V_DDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±8000	V
		Charged device model (CDM), per AEC Q100-011		±1250
		Machine model (MM)		±250
		(IEC 61000-4-2, powered-up only) R_D = 330 Ω, C_S = 150 pF	Air Discharge (Pin 16 and 17)	±15000	V
		(IEC 61000-4-2, powered-up only) R_D = 330 Ω, C_S = 150 pF	Contact Discharge (Pin 16 and 17)	±8000
		(ISO 10605) R_D = 330 Ω, C_S = 150 pF/330 pF R_D = 2 kΩ, C_S = 150 pF/330 pF	Air Discharge (Pin 16 and 17)	±15000
			Contact Discharge (Pin 16 and 17)	±8000

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
Supply Voltage (V_DD33)		3	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)⁽²⁾	Connect V_DDIO to 3.3 V and use 3.3-V IOs	3	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)⁽²⁾	Connect V_DDIO to 1.8 V and use 1.8-V IOs	1.71	1.8	1.89	V
Operating Free Air Temperature (T_A)		−40	+25	+105	°C
PCLK Frequency		5		85	MHz
Supply Noise⁽¹⁾				100	mV_P-P

(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V_DD33 and V_DDIOsupplies with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

(2) V_DDIO < V_DD33 + 0.3 V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90UH927Q-Q1	UNIT
		RTA (WQFN)
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	29.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.4
R_θJB	Junction-to-board thermal resistance	5.1
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	5.1
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS		PIN/FREQ.	MIN	TYP	MAX	UNIT
LVCMOS I/O
V_IH	High Level Input Voltage	V_DDIO = 3.0 V to 3.6 V⁽⁴⁾		PDB	2.0		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 V to 3.6 V⁽⁴⁾			GND		0.8	V
I_IN	Input Current	V_IN = 0 V or V_DDIO = 3.0 V to 3.6 V⁽⁴⁾			−15	±1	+15	μA
V_IH	High Level Input Voltage	V_DDIO = 3.0 V to 3.6 V		GPIO[1:0] I2S_CLK I2S_WC I2S_D [A,B,C,D] LFMODE MAPSEL BKWD REPEAT	2.0		V_DDIO	V
V_IH	High Level Input Voltage	V_DDIO = 1.71 V to 1.89 V			0.65× V_DDIO		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 V to 3.6 V			GND		0.8	V
V_IL	Low Level Input Voltage	V_DDIO = 1.71 V to 1.89 V			GND		0.35* V_DDIO	V
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 3.0 V to 3.6 V		−15	±1	+15	μA
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 1.71 V to 1.89 V		−15	±1	+15	μA
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 3.0 V to 3.6 V	GPIO[3:0], GPO_REG [8:5]	2.4		V_DDIO	V
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 1.71 V to 1.89 V		V_DDIO - 0.45		V_DDIO	V
V_OL	Low Level Output Voltage	I_OL = +4 mA	V_DDIO = 3.0 V to 3.6 V		GND		0.4	V
V_OL	Low Level Output Voltage		V_DDIO = 1.71 V to 1.89 V		GND		0.45	V
I_OS	Output Short Circuit Current⁽⁵⁾	V_OUT = 0 V				−55		mA
I_OZ	TRI-STATE® Output Current	V_OUT = 0 V or V_DDIO, PDB = L,			−15		+15	μA
FPD-LINK LVDS RECEIVER
V_TH	Threshold High Voltage	V_CM = 1.2 V		RxCLKIN± RxIN[3:0]±			+100	mV
V_TL	Threshold Low Voltage				−100			mV
\|V_ID\|	Differential Input Voltage Swing				200		600	mV
V_CM	Common Mode Voltage				0	1.2	2.4	V
I_IN	Input Current				−10		+10	μA
FPD-LINK III CML DRIVER
V_ODp-p	Differential Output Voltage (DOUT+) – (DOUT-)	R_L = 100 Ω		DOUT±	800	1000	1200	mV_p-p
ΔV_OD	Output Voltage Unbalance					1	50	mV
V_OS	Offset Voltage – Single-ended	R_L = 100 Ω				2.5-0.25* V_{ODp-p (TYP)}		V
ΔV_OS	Offset Voltage Unbalance Single-ended					1	50	mV
I_OS	Output Short Circuit Current	DOUT+/- = 0V, PDB = L or H						mA
R_T	Internal Termination Resistance - Differential				80	100	120	Ω
SUPPLY CURRENT
I_DD1	Supply Current R_L = 100Ω, PCLK = 85MHz	Checkerboard Pattern		V_DD33= 3.6 V		135	160	mA
I_DDIO1				V_DDIO = 3.6 V		100	500	μA
I_DDIO1				V_DDIO = 1.89 V		200	600	μA
I_DD2		Random Pattern PRBS7		V_DD33= 3.6 V		133		mA
I_DDIO2				V_DDIO = 3.6 V		100		μA
I_DDIO2				V_DDIO = 1.89 V		100		μA
I_DDS	Supply Current — Remote Auto Power Down	reg_0x01[7]=1, Back channel Idle		V_DD33 = 3.6 V		1.2	2.4	mA
I_DDIOS				V_DDIO = 3.6 V		4	30	μA
I_DDIOS				V_DDIO = 1.89 V		5	30	μA
I_DDZ	Supply Current — Power Down	PDB = 0 V, All other LVCMOS inputs = 0 V		V_DD33 = 3.6 V		1	2.2	mA
I_DDIOZ				V_DDIO = 3.6 V		8	20	μA
I_DDIOZ				V_DDIO = 1.89 V		4	20	μA

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(2) Typical values represent most likely parametric norms at V_DD33 = 3.3V, V_DDIO = 1.8V or 3.3V, T_A = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD and ΔV_OD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50 MHz.

(4) PDB is specified to 3.3-V LVCMOS only and must be driven or pulled up to V_DD33 or to V_DDIO ≥ 3.0 V

(5) I_OS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
FPD-LINK LVDS INPUT
t_RSP	Receiver Strobe Position	See Figure 4	RxCLKIN±, RXIN[3:0]±	0.25	0.5	0.75	UI
FPD-LINK III CML I/O
t_LHT	CML Output Low-to-High Transition Time	See Figure 3	DOUT+, DOUT-		100	140	ps
t_HLT	CML Output High-to-Low Transition Time	See Figure 3	DOUT+, DOUT-		100	140	ps
t_PLD	Serializer PLL Lock Time	See Figure 5, ⁽⁴⁾	PCLK = 5 MHz to 85 MHz			5	ms
t_SD	Delay — Latency	See Figure 6			146*T		ns
t_TJIT	Output Total Jitter, Bit Error Rate ≤1E-9, see Figure 7, ⁽⁵⁾⁽⁶⁾⁽⁷⁾⁽⁸⁾⁽⁹⁾	Checkerboard Pattern PCLK=5 MHz, see Figure 8	RxCLKIN±		0.17	0.2	UI
t_TJIT		Checkerboard Pattern PCLK=85 MHz, see Figure 8	RxCLKIN±		0.26	0.29	UI
t_IJIT	Input Jitter Tolerance, Bit Error Rate ≤1E-9 ⁽⁸⁾⁽¹⁰⁾	f/40 < Jitter Freq < f/20, DES = DS90UH926Q-Q1	RxCLKIN±, f = 78 MHz		0.6		UI
t_IJIT	Input Jitter Tolerance, Bit Error Rate ≤1E-9 ⁽⁸⁾⁽¹⁰⁾	f/40 < Jitter Freq < f/20, DES = DS90UH928Q-Q1	RxCLKIN±, f = 78 MHz		0.5		UI
I²S RECEIVER
T_I2S	I²S Clock Period, see Figure 10, ⁽⁷⁾⁽¹¹⁾	RxCLKIN± f=5 MHz to 85 MHz	I2S_CLK, PCLK = 5 MHz to 85 MHz		>4 / PCLK or >77		ns
T_HC	I²S Clock High Time, see Figure 10, ⁽¹¹⁾		I2S_CLK	0.35			T_I2S
T_LC	I²S Clock Low Time, see Figure 10, ⁽¹¹⁾		I2S_CLK	0.35			T_I2S
t_sr	I²S Set-up Time		I2S_WC I2S_D[A,B,C,D]	0.2			T_I2S
t_htr	I²S Hold Time		I2S_WC I2S_D[A,B,C,D]	0.2			T_I2S
OTHER I/O
t_GPIO,FC	GPIO Pulse Width, Forward Channel		GPIO[3:0], PCLK = 5 MHz to 85 MHz	>2/PCLK			s
t_GPIO,BC	GPIO Pulse Width, Back Channel		GPIO[3:0]	20			µs

(4) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.

(5) Output jitter specs are dependent upon the input clock jitter at the SER.

(6) UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.

(7) Specification is ensured by design and is not tested in production.

(8) Specification is ensured by characterization and is not tested in production.

(9) t_TJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN±.

(10) Jitter Frequency is specified in conjunction with DS90UH928Q-Q1 PLL bandwidth.

(11) I²S specifications for t_LC and t_HC pulses must each be greater than 2 PCLK periods to ensure sampling and supersedes the 0.35*T_{I2S_CLK} requirement. t_LC and t_HC must be longer than the greater of either 0.35*T_{I2S_CLK} or 2*PCLK.

6.7 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Level	SDA and SCL	0.7* V_DDIO		V_DD33	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.3* V_DD33	V
V_HY	Input Hysteresis			>50		mV
V_OL		SDA or SCL, IOL = 1.25 mA	0		0.36	V
I_in		SDA or SCL, Vin = V_DDIO or GND	-10		+10	µA
C_in	Input Capacitance	SDA or SCL		<5		pF

6.8 Recommended Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

			MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	Standard Mode	0	100	kHz
f_SCL	SCL Clock Frequency	Fast Mode	0	400	kHz
t_LOW	SCL Low Period	Standard Mode	4.7		µs
t_LOW	SCL Low Period	Fast Mode	1.3		µs
t_HIGH	SCL High Period	Standard Mode	4.0		µs
t_HIGH	SCL High Period	Fast Mode	0.6		µs
t_HD;STA	Hold time for a start or a repeated start condition, see Figure 9	Standard Mode	4.0		µs
t_HD;STA		Fast Mode	0.6		µs
t_SU:STA	Set Up time for a start or a repeated start condition, see Figure 9	Standard Mode	4.7		µs
t_SU:STA		Fast Mode	0.6		µs
t_HD;DAT	Data Hold Time, see Figure 9	Standard Mode	0	3.45	µs
t_HD;DAT	Data Hold Time, see Figure 9	Fast Mode	0	0.9	µs
t_SU;DAT	Data Set Up Time, see Figure 9	Standard Mode	250		ns
t_SU;DAT	Data Set Up Time, see Figure 9	Fast Mode	100		ns
t_SU;STO	Set Up Time for STOP Condition, see Figure 9	Standard Mode	4.0		µs
t_SU;STO	Set Up Time for STOP Condition, see Figure 9	Fast Mode	0.6		µs
t_BUF	Bus Free Time Between STOP and START, see Figure 9	Standard Mode	4.7		µs
t_BUF	Bus Free Time Between STOP and START, see Figure 9	Fast Mode	1.3		µs
t_r	SCL & SDA Rise Time, see Figure 9	Standard Mode		1000	ns
t_r	SCL & SDA Rise Time, see Figure 9	Fast Mode		300	ns
t_f	SCL & SDA Fall Time, see Figure 9	Standard Mode		300	ns
t_f	SCL & SDA Fall Time, see Figure 9	Fast mode		300	ns

6.9 Timing Requirements

			NOM	UNIT
t_R	SDA RiseTime – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, see Figure 9	430	ns
t_F	SDA Fall Time – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, see Figure 9	20	ns
t_SU;DAT	Set Up Time — READ	See Figure 9	560	ns
t_HD;DAT	Hold Up Time — READ	See Figure 9	615	ns
t_SP	Input Filter		50	ns