ZHCSDZ6D July 2012 – July 2015 DS90UB913Q-Q1 , DS90UB914Q-Q1
PRODUCTION DATA.
Figure 5. Bidirectional Control Bus Timing
Figure 6. Worst Case Test Pattern
Figure 7. Serializer CML Output Load and Transition Times
Figure 8. Serializer CML Output Load and Transition Times
Figure 9. Serializer VOD Diagram
Figure 10. Serializer VOD Diagram
Figure 11. Differential Vswing Diagram
Figure 12. Serializer Input Clock Transition Times
Figure 13. Serializer Set-Up and Hold Times
Figure 14. Serializer PLL Lock Time
Figure 15. Serializer Delay
Figure 16. Deserializer Data Lock Time
Figure 17. Deserializer LVCMOS Output Load and Transition Times
Figure 18. Deserializer Delay
Figure 19. Deserializer Output Set-Up and Hold Times
Figure 20. CML Output Driver
Figure 21. Output State (Set-Up and Hold) Times
Figure 22. Typical Serializer Jitter Transfer Function at 100 MHz
Figure 23. Typical Deserializer Input Jitter Tolerance Curve at 1.4-Gbps Line Rate
Figure 24. Spread Spectrum Clock Output Profile