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SNLS340E November 2011 – November 2015 DS100KR800

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

NJY|54
- MPQS027A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

		MIN	MAX	UNIT
Supply voltage (VDD = 2.5-V mode)		–0.5	2.75	V
Supply voltage (VIN = 3.3-V mode)		–0.5	4	V
LVCMOS input or output voltage		–0.5	4	V
CML input voltage		–0.5	(VDD + 0.5)	V
CML input current		–30	30	ma
Junction temperature			125	°C
Lead temperature	Soldering (4 sec.)⁽²⁾		260	°C
Derate NJY0054A package			52.6	mW/°C
Storage temperature, T_stg		–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For soldering specifications: see product folder at SNOA549.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±3000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000
		Machine model, STD - JESD22-A115-A	±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
Supply voltage	2.5-V mode	2.375	2.5	2.625	V
Supply voltage	3.3-V mode	3.0	3.3	3.6	V
Ambient temperature		–40	25	85	°C
SMBus (SDA, SCL)				3.6	V
Supply noise up to 50 MHz⁽¹⁾				100	mVp-p

(1) Allowed supply noise (mVp-p sine wave) under typical conditions.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS100KR800	UNIT
		NJY (WQFN)
		54 PINS
R_θJA	Junction-to-ambient thermal resistance, No Airflow, 4-layer JEDEC	26.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10.8	°C/W
R_θJB	Junction-to-board thermal resistance	4.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	4.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

See ⁽³⁾⁽²⁾

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
POWER
PD	Power dissipation	EQ enabled, VOD = 1 Vp-p, INPUT_EN = 1, RESET = 0	VDD = 2.5-V supply		500	700	mW
PD	Power dissipation	EQ enabled, VOD = 1 Vp-p, INPUT_EN = 1, RESET = 0	VIN = 3.3-V supply		660	900	mW
LVCMOS / LVTTL DC SPECIFICATIONS
V_ih	High level Input voltage	3.3-V mode operation (VIN = 3.3 V)		2		3.6	V
V_il	Low level Input voltage	3.3-V mode operation (VIN = 3.3 V)		0		0.8	V
V_oh	High level output voltage (ALL_DONE pin)	I_oh = –4 mA		2			V
V_ol	Low level output voltage (ALL_DONE pin)	I_ol = 4 mA				0.4	V
I_ih	Input high current (RESET pin)	VIN = 3.6 V, LVCMOS = 3.6 V		–15		15	µA
I_ih	Input high current with internal resistors (4–level input pin)	VIN = 3.6 V, LVCMOS = 3.6 V		20		150	µA
I_il	Input low current (RESET pin)	VIN = 3.6 V, LVCMOS = 0 V		–15		15	µA
I_il	Input low current with internal resistors (4–level input pin)	VIN = 3.6 V, LVCMOS = 0 V		–160		–40	µA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RL_rx-diff	RX package pins plus Si differential return loss	0.05 GHz - 7.5 GHz			–15		dB
RL_rx-diff	RX package pins plus Si differential return loss	7.5 GHz - 15 GHz			–5		dB
RLrx-cm	Common-mode RX return loss	0.05 GHz - 5 GHz			–10		dB
Zrx-dc	RX DC common-mode impedance	Tested at VDD = 0		40	50	60	Ω
Zrx-diff-dc	RX DC differential mode impedance	Tested at VDD = 0		80	100	120	Ω
Vrx-diff-dc	Differential RX peak-to-peak voltage	Tested at pins		0.6		1.2	V
Vrx-signal-det-diff-pp	Signal detect assert level for active data signal	SD_TH = F (float), 0101 pattern at 8 Gbps			180		mVp-p
Vrx-idle-det-diff-pp	Signal detect deassert level for electrical idle	SD_TH = F (float), 0101 pattern at 8 Gbps			110		mVp-p
HIGH SPEED OUTPUTS
V_tx-diff-pp	Output voltage differential swing	Differential measurement with Out_n+ and OUT_n-, terminated by 50Ω to GND, AC-Coupled, VID = 1 Vp-p, DEM0 = 1, DEM1 = 0		0.8	1	1.2	Vp-p
V_{tx-de-ratio_3.5}	TXde-emphasis ratio	VOD = 1 Vp-p, DEM0 = 0, DEM1 = R			−3.5		dB
V_{tx-de-ratio_6}	TX de-emphasis ratio	VOD = 1 Vp-p, DEM0 = R, DEM1= R			–6		dB
t_TX-DJ	Deterministic jitter	VID = 800 mV, PRBS15 pattern, 8.0 0.05 Gbps, VOD = 1 V, UIpp EQ = 0x00, DE = 0 dB (no input or output trace loss)			0.05		UIpp
t_TX-RJ	Random jitter	VID = 800 mV, 0101 pattern, 8.0 Gbps, 0.3 VOD = 1 V, ps RMS EQ = 0x00, DE = 0 dB, (no input or output trace loss)			0.3		ps RMS
T_TX-RISE-FALL	Transmitter rise/fall time	20% to 80% of differential output voltage		35	45		ps
T_RF-MISMATCH	Transmitter rise/fall mismatch	20% to 80% of differential output voltage			0.01	0.1	UI
RL_TX-DIFF	Differential return loss	0.05 GHz - 7.5 GHz			–15		dB
RL_TX-DIFF	Differential return loss	7.5 GHz - 15 GHz			–5		dB
RL_TX-CM	Common-mode return loss	0.05 GHz - 5 GHz			–10		dB
Z_TX-DIFF-DC	DC differential TX impedance				100		Ω
V_TX-CM-AC-PP	TX AC common-mode voltage	VOD = 1 Vp-p, DEM0 = 1, DEM1 = 0				100	mVpp
I_TX-SHORT	Transmitter short circuit current-limit	Total current the transmitter can supply when shorted to VDD or GND			20		mA
T_PDEQ	Differential propagation delay	EQ = 00, ⁽⁴⁾			200		ps
T_LSK	Lane-to-lane skew	T = 25°C, VDD = 2.5 V			25		ps
T_PPSK	Part-to-part propagation delay skew	T = 25°C, VDD = 2.5 V			40		ps
EQUALIZATION
DJE1	Residual deterministic jitter at 10.3 Gbps	35-in 4 mil FR4, VID = 0.8 Vp-p, PRBS15, EQ = 1F'h, DEM = 0 dB			0.3		UI
DJE2	Residual deterministic jitter at 10.3 Gbps	10 meters 30 awg cable, VID = 0.8 Vp-p, PRBS15, EQ = 2F'h, DEM = 0 dB			0.3		UI
DE-EMPHASIS
DJD1	Residual deterministic jitter at 10.3 Gbps	20-in 4 mil FR4, VID = 0.8 Vp-p, PRBS15, EQ = 00, VOD = 1 Vp-p, DEM = −9 dB			0.1		UI

(1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(3) Ensured by device characterization.

(4) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays.

6.6 Electrical Characteristics – Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL	Data, clock input low voltage				0.8	V
V_IH	Data, clock input high voltage		2.1		3.6	V
I_PULLUP	Current through pullup resistor or current source	High power specification	4			mA
V_DD	Nominal bus voltage		2.375		3.6	V
I_LEAK-Bus	Input leakage per bus segment	See ⁽¹⁾	–200		200	µA
I_LEAK-Pin	Input leakage per device pin			–15		µA
C_I	Capacitance for SDA and SCL	See ⁽¹⁾ ⁽²⁾			10	pF
R_TERM	External termination resistance pull to V_DD = 2.5 V ± 5% OR 3.3 V ± 10%	Pullup V_DD = 3.3 V, See ⁽¹⁾ ⁽²⁾ ⁽³⁾		2000		Ω
R_TERM		Pullup V_DD = 2.5 V, See ⁽¹⁾ ⁽²⁾ ⁽³⁾		1000		Ω

(1) Recommended value.

(2) Recommended maximum capacitance load per bus segment is 400pF.

(3) Maximum termination voltage should be identical to the device supply voltage.

6.7 Timing Requirements – Serial Bus Interface Timing Specifications

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
FSMB	Bus operating frequency	ENSMB = VDD (slave mode)			400	kHz
FSMB	Bus operating frequency	ENSMB = FLOAT (master mode)	280	400	520	kHz
T_BUF	Bus free time between stop and start condition		1.3			µs
T_HD:STA	Hold time after (repeated) start condition. After this period, the first clock is generated.	At I_PULLUP, maximum	0.6			µs
T_SU:STA	Repeated start condition set-up time		0.6			µs
T_SU:STO	Stop condition set-up time		0.6			µs
T_HD:DAT	Data hold time		0			ns
T_SU:DAT	Data set-up time		100			ns
T_LOW	Clock low period		1.3			µs
T_HIGH	Clock high period	See ⁽¹⁾	0.6		50	µs
t_F	Clock/Data fall time	See ⁽¹⁾			300	ns
t_R	Clock/Data rise time	See ⁽¹⁾			300	ns
t_POR	Time in which a device must be operational after power-on reset	See ⁽¹⁾ ⁽²⁾			500	ms

(1) Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.

(2) Ensured by Design. Parameter not tested in production.

Figure 1. CML Output and Rise and Fall Transition Time

Figure 2. Propagation Delay Timing Diagram

Figure 3. SMBus Timing Parameters

6.8 Typical Characteristics

6.8.1 Electrical Performance

Figure 4. Power Dissipation (PD) vs Output Differential Voltage (VOD)

Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature

Figure 5. Output Differential Voltage (VOD = 1 Vp-p) vs Supply Voltage (VDD)