ZHCSWR1H December 2009 – July 2024 DRV8412
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION | ||||||
| VREG | Voltage regulator, only used as a reference node | VDD = 12 V | 2.95 | 3.3 | 3.65 | V |
| IVDD | VDD supply current | Idle, reset mode | 9 | 12 | mA | |
| Operating, 50% duty cycle | 10.5 | |||||
| IGVDD_X | Gate supply current per half-bridge | Reset mode | 1.7 | 2.5 | mA | |
| Operating, 50% duty cycle | 8 | |||||
| IPVDD_X | Half-bridge X (A, B, C, or D) idle current | Reset mode | 0.7 | 1 | mA | |
| OUTPUT STAGE | ||||||
| RDS(on) | MOSFET drain-to-source resistance, low side (LS) | TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance | 110 | m? | ||
| MOSFET drain-to-source resistance, high side (HS) | TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance | 110 | ||||
| VF | Diode forward voltage drop | TJ = 25°C - 125°C, IO = 5 A | 1 | V | ||
| tR | Output rise time | Resistive load, IO = 5 A | 14 | ns | ||
| tF | Output fall time | Resistive load, IO = 5 A | 14 | |||
| tPD_ON | Propagation delay when FET is on | Resistive load, IO = 5 A | 38 | |||
| tPD_OFF | Propagation delay when FET is off | Resistive load, IO = 5 A | 38 | |||
| tDT | Dead time between HS and LS FETs | Resistive load, IO = 5 A | 5.5 | |||
| I/O PROTECTION | ||||||
| Vuvp,G | Gate supply voltage GVDD_X undervoltage protection threshold | 8.5 | V | |||
| Vuvp,hyst(1) | Hysteresis for gate supply undervoltage event | 0.8 | ||||
| OTW(1) | Overtemperature warning | 115 | 125 | 135 | °C | |
| OTWhyst(1) | Hysteresis temperature to reset OTW event | 25 | ||||
| OTSD(1) | Overtemperature shut down | 150 | ||||
| OTE-OTWdifferential(1) | OTE-OTW overtemperature detect temperature difference | 25 | ||||
| OTSDHYST(1) | Hysteresis temperature for FAULT to be released following an OTSD event | 25 | ||||
| IOC | Overcurrent limit protection | Resistor—programmable, nominal, ROCP = 27 k? | 9.7 | A | ||
| IOCT | Overcurrent response time | Time from application of short condition to Hi-Z of affected FET(s) | 250 | ns | ||
| RPD | Internal pulldown resistor at the output of each half-bridge | Connected when RESET_AB or RESET_CD is active to provide bootstrap capacitor charge | 1 | k? | ||
| STATIC DIGITAL SPECIFICATIONS | ||||||
| VIH | High-level input voltage | PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3 | 2 | 3.6 | V | |
| VIH | High-level input voltage | RESET_AB, RESET_CD | 2 | 5.5 | ||
| VIL | Low-level input voltage | PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD | 0.8 | |||
| llkg | Input leakage current | –100 | 100 | μA | ||
| OTW / FAULT | ||||||
| RINT_PU | Internal pullup resistance, OTW to VREG, FAULT to VREG | 20 | 26 | 35 | k? | |
| VOH | High-level output voltage | Internal pullup resistor only | 2.95 | 3.3 | 3.65 | V |
| External pullup of 4.7 k? to 5 V | 4.5 | 5 | ||||
| VOL | Low-level output voltage | IO = 4 mA | 0.2 | 0.4 | ||