ZHCSMP7 November 2021 DRV8231
PRODUCTION DATA
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria.
HSOP (DDA package)
| Layer | 2-layer | 4-layer |
|---|---|---|
| Top Layer | HSOP footprint with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from HSOP thermal pad to bottom layer and internal ground plane (4-layer only). | |
| Layer 2, internal ground plane | N/A | 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, thermally connected to HSOP thermal pad through vias. |
| Layer 3, internal supply plane | N/A | 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, not connected to other layers. |
| Bottom Layer | Ground plane with 1- or 2-oz copper thickness. See Table 9-6 for copper area varied in simulation. Thermally connected to HSOP thermal pad through vias. | 1- or 2-oz copper thickness. Copper area fixed at 4.90 mm × 6.00 mm in simulation. Thermally connected to HSOP thermal pad through vias. |
Figure 9-18 shows an example of the simulated board for the HSOP package. Table 9-6 shows the dimensions of the board that were varied for each simulation.
| Cu area (cm2) | Dimension A (mm) |
|---|---|
| 0.069 | Package thermal pad dimensions |
| 2 | 16.40 |
| 4 | 22.32 |
| 8 | 30.64 |
| 16 | 42.38 |
WSON (DSG package)
| Layer | 2-layer | 4-layer |
|---|---|---|
| Top Layer | WSON footprint with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally connected with vias (2 vias, 1.2-mm spacing, 0.3-mm diameter, 0.025-mm copper plating) from WSON thermal pad to bottom layer and internal ground plane (4-layer only). | |
| Layer 2, internal ground plane | N/A | 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, thermally connected to HSOP thermal pad through vias. |
| Layer 3, internal supply plane | N/A | 1-oz copper thickness, 74.2 mm x 74.2 mm copper area, not connected to other layers. |
| Bottom Layer | Ground plane with 1- or 2-oz copper thickness. See Table 9-8 for copper area varied in simulation. Thermally connected to WSON thermal pad through vias. | 1- or 2-oz copper thickness. Copper area fixed at 2.00 mm × 2.00 mm in simulation. Thermally connected to WSON thermal pad through vias. |
Figure 9-19 shows an example of the simulated board for the WSON package. Table 9-8 shows the dimensions of the board that were varied for each simulation.
| Cu area (mm2) | Dimension A (mm) |
|---|---|
| 0.015 | Package thermal pad dimensions |
| 2 | 15.11 |
| 4 | 20.98 |
| 8 | 29.27 |
| 16 | 40.99 |