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SNLS266E May 2007 – March 2015 DP83848C , DP83848I , DP83848VYB , DP83848YB

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PTB|48
- MPQF244

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

5 Specifications

5.1 Absolute Maximum Ratings ⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply Voltage (V_CC)	–0.5	4.2	V
DC Input Voltage (V_IN)	–0.5	V_CC + 0.5	V
DC Output Voltage (V_OUT)	–0.5	V_CC + 0.5	V
Maximum Die Temperature		121.5	°C
Lead Temperature (TL) (Soldering, 10 sec.)		260	°C
Storage Temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

5.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±4000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Supply voltage (V_CC)		3.3 V ± 0.3	V
Commercial	0	70	°C
Industrial	–40	85
Extended	–40	105
Extreme	–40	125
Power Dissipation (P_D)		267	mW

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		DP83848C/I	DP83848VYB/YB	UNIT
		PT [HLQFP]	PTB [LQFP]
		48 PINS	48 PINS
R_θJA	Junction-to-ambient thermal resistance	73.9	40.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	30.9	25.5
R_θJB	Junction-to-board thermal resistance	37.2	21
ψ_JT	Junction-to-top characterization parameter	2.8	2.7
ψ_JB	Junction-to-board characterization parameter	37	20.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	3.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5.5 DC Specifications

PARAMETER		TEST CONDITIONS	PIN TYPES	MIN	TYP	MAX	UNIT
V_IH	Input High Voltage	Nominal V_CC	I,	2.0			V
V_IH	Input High Voltage	Nominal V_CC	I/O	2.0			V
V_IL	Input Low Voltage		I,			0.8	V
V_IL	Input Low Voltage		I/O			0.8	V
I_IH	Input High Current	V_IN = V_CC	I,			10	µA
I_IH	Input High Current	V_IN = V_CC	I/O			10	µA
I_IL	Input Low Current	V_IN = GND	I,			10	µA
I_IL	Input Low Current	V_IN = GND	I/O			10	µA
V_OL	Output Low	I_OL = 4 mA	O,			0.4	V
V_OL	Voltage	I_OL = 4 mA	I/O			0.4	V
V_OH	Output High	I_OH = –4 mA	O,	V_CC - 0.5			V
V_OH	Voltage	I_OH = –4 mA	I/O	V_CC - 0.5			V
I_OZ	TRI-STATE	V_OUT = V_CC	I/O,			±10	µA
I_OZ	Leakage	V_OUT = GND	O			±10	µA
V_{TPTD_100}	100M Transmit Voltage		PMD Output Pair	0.95	1	1.05	V
V_TPTDsym	100M Transmit Voltage Symmetry		PMD Output Pair			±2%
V_{TPTD_10}	10M Transmit Voltage		PMD Output Pair	2.2	2.5	2.8	V
C_IN1	CMOS Input		I		5		pF
C_IN1	Capacitance		I		5		pF
C_OUT1	CMOS Output		O		5		pF
C_OUT1	Capacitance		O		5		pF
SD_THon	100BASE-TX		PMD Input Pair			1000	mV diff pk-pk
SD_THon	Signal detect turnon threshold		PMD Input Pair			1000	mV diff pk-pk
SD_THoff	100BASE-TX		PMD Input Pair	200			mV diff pk-pk
SD_THoff	Signal detect turnoff threshold		PMD Input Pair	200			mV diff pk-pk
V_TH1	10BASE-T Receive Threshold		PMD Input Pair			585	mV
I_dd100	100BASE-TX		Supply		81		mA
I_dd100	(Full Duplex)		Supply		81		mA
I_dd10	100BASE-TX		Supply		92		mA
I_dd10	(Full Duplex)		Supply		92		mA
I_dd	Power Down Mode	CLK2MAC disabled	Supply		14		mA

5.6 AC Timing Requirements

PARAMETER	DESCRIPTION	NOTES	MIN	TYP	MAX	UNIT
POWER-UP TIMING
T2.1.1	Post Power-Up Stabilization time prior to MDC preamble for register accesses⁽¹⁾	MDIO is pulled high for 32-bit serial management initialization	167			ms
T2.1.1		X1 Clock must be stable for a min. of 167 ms at power up.	167			ms
T2.1.2	Hardware Configuration Latch-in Time from power up⁽¹⁾	Hardware Configuration Pins are described in the Section 4 section.	167			ms
T2.1.2	Hardware Configuration Latch-in Time from power up⁽¹⁾	X1 Clock must be stable for a min. of 167 ms at power up.	167			ms
T2.1.3	Hardware Configuration pins transition to output drivers			50		ns
RESET TIMING
T2.2.1	Post RESET Stabilization time prior to MDC preamble for register accesses⁽²⁾	MDIO is pulled high for 32-bit serial management initialization		3		µs
T2.2.2	Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard)⁽²⁾	Hardware Configuration Pins are described in the Section 4 section		3		µs
T2.2.3	Hardware Configuration pins transition to output drivers			50		ns
T2.2.4	RESET pulse width	X1 Clock must be stable for at min. of 1us during RESET pulse low time.	1			µs
MII SERIAL MANAGEMENT TIMING
T2.3.1	MDC to MDIO (Output) Delay Time		0		30	ns
T2.3.2	MDIO (Input) to MDC Setup Time		10			ns
T2.3.3	MDIO (Input) to MDC Hold Time		10			ns
T2.3.4	MDC Frequency			2.5	25	MHz
100 Mb/s MII TRANSMIT TIMING
T2.4.1	TX_CLK High/Low Time	100 Mb/s Normal mode	16	20	24	ns
T2.4.2	TXD[3:0], TX_EN Data Setup to TX_CLK	100 Mb/s Normal mode	10			ns
T2.4.3	TXD[3:0], TX_EN Data Hold from TX_CLK	100 Mb/s Normal mode	0			ns
100 Mb/s MII RECEIVE TIMING
T2.5.1	RX_CLK High/Low Time⁽³⁾	100 Mb/s Normal mode	16	20	24	ns
T2.5.2	RX_CLK to RXD[3:0], RX_DV, RX_ER Delay	100 Mb/s Normal mode	10		30	ns
100BASE-TX MII TRANSMIT PACKET LATENCY TIMING
T2.6.1	TX_CLK to PMD Output Pair Latency⁽⁴⁾	100BASE-TX mode		6		bits
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING
T2.7.1	TX_CLK to PMD Output Pair Deassertion⁽⁵⁾	100BASE-TX mode		5		bits
100BASE-TX TRANSMIT TIMING (t_R/F and Jitter)
T2.8.1	100 Mb/s PMD Output Pair t_R and t_F⁽⁷⁾		3	4	5	ns
T2.8.1	100 Mb/s t_R and t_F Mismatch⁽⁶⁾⁽⁷⁾				500	ps
T2.8.2	100 Mb/s PMD Output Pair Transmit Jitter				1.4	ns
100BASE-TX RECEIVE PACKET LATENCY TIMING⁽¹⁰⁾
T2.9.1	Carrier Sense ON Delay⁽⁸⁾	100 Mb/s Normal mode⁽⁹⁾		20		bits
T2.9.2	Receive Data Latency	100 Mb/s Normal mode⁽⁹⁾		24		bits
100BASE-TX RECEIVE PACKET DEASSERTION TIMING
T2.10.1	Carrier Sense OFF Delay⁽¹¹⁾	100 Mb/s Normal mode⁽⁹⁾		24		bits
10 Mb/s MII TRANSMIT TIMING⁽¹²⁾
T2.11.1	TX_CLK High/Low Time	10 Mb/s MII mode	190	200	210	ns
T2.11.2	TXD[3:0], TX_EN Data Setup to TX_CLK fall	10 Mb/s MII mode	25			ns
T2.11.3	TXD[3:0], TX_EN Data Hold from TX_CLK rise	10 Mb/s MII mode	0			ns
10 Mb/s MII RECEIVE TIMING
T2.12.1	RX_CLK High/Low Time⁽¹³⁾		160	200	240	ns
T2.12.2	RX_CLK TO RXD[3:0}, RX_DV Delay	10 Mb/s MII mode	100			ns
T2.12.3	RX_CLK rising edge delay from RXD[3:0], RX_DV Valid	10 Mb/s MII mode	100			ns
10 Mb/s SERIAL MODE (SNI) TRANSMIT TIMING
T2.13.1	TX_CLK High Time	10 Mb/s Serial mode (SNI)	20	25	30	ns
T2.13.2	TX_CLK Low Time	10 Mb/s Serial mode (SNI)	70	75	80	ns
T2.13.3	TXD_0, TX_EN Data Setup to TX_CLK rise	10 Mb/s Serial mode (SNI)	25			ns
T2.13.4	TXD_0, TX_EN Data Hold from TX_CLK rise	10 Mb/s Serial mode (SNI)	0			ns
10 Mb/s SERIAL MODE (SNI) RECEIVE TIMING
T2.14.1	RX_CLK High/Low Time⁽¹⁴⁾		35	50	65	ns
T2.14.2	RX_CLK fall to RXD_0, RX_DV Delay	10 Mb/s Serial mode (SNI)	–10		10	ns
10BASE-T TRANSMIT TIMING (START OF PACKET)
T2.15.1	Transmit Output Delay from the	10 Mb/s MII mode⁽¹⁵⁾		3.5		bits
T2.15.1	Falling Edge of TX_CLK	10 Mb/s MII mode⁽¹⁵⁾		3.5		bits
T2.15.2	Transmit Output Delay from the	10 Mb/s Serial mode (SNI)⁽¹⁵⁾		3.5		bits
T2.15.2	Rising Edge of TX_CLK	10 Mb/s Serial mode (SNI)⁽¹⁵⁾		3.5		bits
10BASE-T TRANSMIT TIMING (END OF PACKET)
T2.16.1	End of Packet High Time		250	300		ns
T2.16.1	(with '0' ending bit)		250	300		ns
T2.16.2	End of Packet High Time		250	300		ns
T2.16.2	(with '1' ending bit)		250	300		ns
10BASE-T RECEIVE TIMING (START OF PACKET)⁽¹⁷⁾
T2.17.1	Carrier Sense Turnon Delay (PMD Input Pair to CRS)			630	1000	ns
T2.17.2	RX_DV Latency⁽¹⁶⁾			10		bits
T2.17.3	Receive Data Latency	Measurement shown from SFD		8		bits
10BASE-T RECEIVE TIMING (END OF PACKET)
T2.18.1	Carrier Sense Turn Off Delay				1	µs
10 Mb/s HEARTBEAT TIMING
T2.19.1	CD Heartbeat Delay	10 Mb/s half-duplex mode		1200		ns
T2.19.2	CD Heartbeat Duration	10 Mb/s half-duplex mode		1000		ns
10 Mb/s JABBER TIMING
T2.20.1	Jabber Activation Time			85		ms
T2.20.2	Jabber Deactivation Time			500		ms
10BASE-T NORMAL LINK PULSE TIMING⁽¹⁸⁾
T2.21.1	Pulse Width			100		ns
T2.21.2	Pulse Period			16		ms
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING⁽¹⁸⁾
T2.22.1	Clock, Data Pulse Width			100		ns
T2.22.2	Clock Pulse to Clock Pulse			125		µs
T2.22.2	Period			125		µs
T2.22.3	Clock Pulse to Data Pulse	Data = 1		62		µs
T2.22.3	Period	Data = 1		62		µs
T2.22.4	Burst Width			2		ms
T2.22.5	FLP Burst to FLP Burst Period			16		ms
100BASE-TX SIGNAL DETECT TIMING⁽¹⁹⁾
T2.23.1	SD Internal Turnon Time				1	ms
T2.23.2	SD Internal Turnoff Time				350	µs
100 Mb/s INTERNAL LOOPBACK TIMING
T2.24.1	TX_EN to RX_DV Loopback⁽²¹⁾	100 Mb/s internal loopback mode⁽²⁰⁾			240	ns
10 Mb/s INTERNAL LOOPBACK TIMING
T2.25.1	TX_EN to RX_DV Loopback⁽²¹⁾	10 Mb/s internal loopback mode			2	µs
RMII TRANSMIT TIMING
T2.26.1	X1 Clock Period	50 MHz Reference Clock		20		ns
T2.26.2	TXD[1:0], TX_EN, Data Setup to X1 rising		4			ns
T2.26.3	TXD[1:0], TX_EN, Data Hold from X1 rising		2			ns
T2.26.4	X1 Clock to PMD Output Pair Latency	From X1 Rising edge to first bit of symbol		17		bits
RMII RECEIVE TIMING
T2.27.1	X1 Clock Period	50 MHz Reference Clock		20		ns
T2.27.2	RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising⁽²²⁾⁽²³⁾⁽²⁴⁾		2		14	ns
T2.27.3	CRS ON delay (100Mb)	From JK symbol on PMD Receive Pair to initial assertion of CRS_DV		18.5		bits
T2.27.4	CRS OFF delay (100Mb)	From TR symbol on PMD Receive Pair to initial deassertion of CRS_DV		27		bits
T2.27.5	RXD[1:0] and RX_ER latency (100Mb)	From symbol on Receive Pair. Elasticity buffer set to default value (01)		38		bits
ISOLATION TIMING
T2.28.1	From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode				100	µs
T2.28.2	From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode				500	µs
25 MHz_OUT TIMING
T2.29.1	25 MHz_OUT High/Low Time⁽²⁵⁾	MII mode		20		ns
T2.29.1	25 MHz_OUT High/Low Time⁽²⁵⁾	RMII mode		10		ns
T2.29.2	25 MHz_OUT propagation delay⁽²⁵⁾	Relative to X1			8	ns
100 Mb/s X1 TO TX_CLK TIMING
T2.30.1	X1 to TX_CLK delay⁽²⁶⁾	100 Mb/s Normal mode	0		5	ns

(1) In RMII Mode, the minimum Post Power-up Stabilization and Hardware Configuration Latch-in times are 84ms.

(2) It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

(3) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(4) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(5) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(6) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times

(7) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude

(8) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(9) 1 bit time = 10 ns in 100 Mb/s mode.

(10) PMD Input Pair voltage amplitude is greater than the Signal Detect Turnon Threshold Value.

(11) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(12) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK.

(13) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(14) RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(15) 1 bit time = 100 ns in 10 Mb/s.

(16) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV

(17) 1 bit time = 100 ns in 10 Mb/s mode.

(18) These specifications represent transmit timings.

(19) The signal amplitude on PMD Input Pair must be TP-PMD compliant.

(20) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550µs “dead-time”.

(21) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

(22) Per the RMII Specification, output delays assume a 25pF load.

(23) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion.

(24) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.

(25) 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.

(26) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.