9.2.1.2.1 Series and Parallel Resonant Capacitor Selection

Shown in Figure 33, the capacitors C1 (series) and C2 (parallel) make up the dual resonant circuit with the receiver coil. These two capacitors must be sized correctly per the WPC v1.2 specification. Figure 33 shows the equivalent circuit of the dual resonant circuit:

Figure 33. Dual Resonant Circuit with the Receiver Coil

The power receiver design requirements in volume 1 of the WPC v1.2 specification highlights in detail the sizing requirements. To summarize, the receiver designer will be required take inductance measurements with a fixed test fixture. The test fixture is shown in Figure 34:

Figure 34. WPC v1.2 Receiver Coil Test Fixture for the Inductance Measurement Ls’

The primary shield is to be 50 mm × 50 mm × 1 mm of Ferrite material PC44 from TDK Corp. The gap (dZ) is to be 3.4 mm. The receiver coil, as it will be placed in the final system (for example, the back cover and battery must be included if the system calls for this), is to be placed on top of this surface and the inductance is to be measured at 1-V RMS and a frequency of 100 kHz. This measurement is termed Ls’. The measurement termed Ls is the free-space inductance. Each capacitor can then be calculated using Equation 6:

Equation 6.

Where f_S is 100 kHz +5/–10% and f_D is 1 MHz ±10%. C₁ must be chosen first prior to calculating C₂. The quality factor must be greater than 77 and can be determined by Equation 7:

Equation 7.

Where R is the DC resistance of the receiver coil. All other constants are defined above.

For this application, we will design with an inductance measurement (L) of 11 µH and an Ls' of 16 µH with a DC resistance of 191 mΩ. Plugging Ls' into Equation 6 above, we get a value for C₁ to be 158.3 nF. The range on the capacitance is about 144 nF to 175 nF. To build the resulting value, the optimum solution is usually found with 3 capacitors in parallel. This allows for more precise selection of values, lower effective resistance and better thermal results. To get 158 nF, choose from standard values. In this case, the values are 68 nF, 47 nF and 39 nF for a total of 154 nF. Well in the required range. Now that C₁ is chosen, the value of C₂ can be calculated. The result of this calculation is 2.3 nF. The practical solution for this is 2 capacitors, a 2.2 nF capacitor and a 100 pF capacitor. In all cases, these capacitors must have at least a 25-V rating. Solving for the quality factor (Q) this solution shows a rating over 500.

9.2.1.2.2 COMM, CLAMP and BOOT Capacitors

For most applications, the COMM, CLAMP and BOOT capacitors will be chosen to match the Evaluation Module.

The BOOT capacitors are used to allow the internal rectifier FETs to turn on and off properly. These capacitors are on the AC1 or AC2 lines to the Boot nodes and should have a minimum of 10-V rating. A 10-nF capacitor with a 10-V rating is chosen.

The CLAMP capacitors are used to aid the clamping process to protect against overvoltage. Choosing a 0.47-µF capacitor with a 25-V rating is appropriate for most applications.

The COMM capacitors are used to facilitate the communication from the RX to the TX. This selection can vary a bit more than the BOOT and CLAMP capacitors. In general, a 22-nF capacitor is recommended. Based on the results of testing of the communication robustness, a change to a 47-nF capacitor may be in order. The larger the capacitor the larger the deviation will be on the coil which sends a stronger signal to the TX. This also decreases the efficiency somewhat. In this case, choose the 22-nF capacitor with the 25-V rating.

9.2.1.2.3 Charging and Termination Current

The Design Requirements show an 800-mA charging current and an 80-mA termination current.

Setting the charge current (I_BULK) is done by selecting the R₁ and R_FOD. Solving Equation 1 results in R_ILIM of 393 Ω. Setting R_FOD to 200 Ω as a starting point before the FOD calibration is recommended. This leaves 205 Ω for R₁. Using standard resistor values (or resistors in series / parallel) can improve accuracy.

Setting the termination current is done with Equation 2. Because 80 mA is 10% of the I_BULK (800mA), the R_TERM is calculated as (240 * 10) or 2.4 kΩ.

9.2.1.2.4 Adapter Enable

The AD pin will be tied to the external USB power source to allow for an external source to power the system. AD_EN is tied to the gate of Q1 (CSD75205W1015). This allows the bq51050B to sense when power is applied to the AD pin. The EN2 pin controls whether the wired source will be enabled or not. EN2 is tied to the system host to allow it to control the use of the USB power. If wired power is enabled and present, the AD pin will disable the BAT output and then enable Q1 through the AD_EN pin. An external charger is required to take control of the battery charging.

9.2.1.2.5 Charge Indication and Power Capacitors

The CHG pin is open-drain. D₁ and R₄ are selected as a 2.1-V forward bias capable of 2 mA and a 100-Ω current-limiting resistor.

RECT is used to smooth the internal AC to DC conversion. Two 10-µF capacitors and a 0.1-µF capacitor are chosen. The rating is 25 V.

BAT capacitors are 1.0 µF and 0.1 µF.

9.2.2.2.1 Blocking Back-Back FET

Q1 is recommended to eliminate the potential for both wired and wireless systems to drive current to the simultaneously. The charge current and DC voltage level will set up parmerters for the blocking FET. The requirements for this system are 1 A for the wired charger and 5 V DC. The CSD75207W15 is chosen for its low RON and small size.

The wired charger in this solution is the bq24040. See the bq24040 datasheet (SLUS941) for specific component selection.