ZHCSNB8A February 2021 – January 2024 BQ25730
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_LWPWR | WDTMR_ADJ | IIN_DPM_AUTO_DISABLE | OTG_ON_CHRGOK | EN_OOA | PWM_FREQ | LOW_PTM_RIPPLE | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_CMP_LATCH | VSYS_UVP_ENZ | EN_LEARN | IADPT_GAIN | IBAT_GAIN | EN_LDO | EN_IIN_DPM | CHRG_INHIBIT |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT |
FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | EN_LWPWR | R/W | 1b | Low Power Mode Enable, under low power mode lowest quiescent current is achieved when only battery exist. It is not recommended to enable low power mode when adapter present. 0b: Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, current/power monitor buffer and comparator follow register setting. 1b: Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. The REGN is off. The PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator and its low power mode PROCHOT profile can be enabled by setting EN_PROCHOT_LPWR bit to 1b. <default at POR> |
| 6-5 | WDTMR_ADJ | R/W | 11b | WATCHDOG Timer Adjust Set maximum delay between consecutive Host write of charge voltage or charge current command. If device does not receive a write on the REG0x04() or the REG0x02() within the watchdog time period, the charger will be suspended by setting the REG0x02() to 0 mA. After expiration, the timer will resume upon the write of REG0x02(), REG0x04() or REG0x00[14:13]. 00b: Disable Watchdog Timer 01b: Enabled, 5 sec 10b: Enabled, 88 sec 11b: Enable Watchdog Timer, 175 sec <default at POR> |
| 4 | IIN_DPM_AUTO_DISABLE | R/W | 0b | IIN_DPM Auto Disable When CELL_BATPRESZ pin is LOW, the charger automatically disables the IIN_DPM function by setting EN_IIN_DPM (REG0x00[1]) to 0. The host can enable IIN_DPM function later by writing EN_IIN_DPM bit (REG0x00[1]) to 1. 0b: Disable this function. IIN_DPM is not disabled when CELL_BATPRESZ goes LOW. <default at POR> 1b: Enable this function. IIN_DPM is disabled when CELL_BATPRESZ goes LOW. |
| 3 | OTG_ON_CHRGOK | R/W | 0b | Add OTG to CHRG_OK Drive CHRG_OK to HIGH when the device is in OTG mode. 0b: Disable <default at POR> 1b: Enable |
| 2 | EN_OOA | R/W | 1b | Out-of-Audio Enable In both forward mode and OTG mode, switching frequency reduces with diminishing load, under extreme light load condition the switching frequency could be lower than 25 kHz which is already in audible frequency range. By configuring EN_OOA=1b, the minimum PFM burst frequency is clamped at around 25 kHz to avoid any audible noise. 0b: No limit of PFM burst frequency 1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise <default at POR> |
| 1 | PWM_FREQ | R/W | 1b | Switching Frequency Selection: Recommend 800 kHz with 2.2 μH, and 400 kHz with 4.7 μH. 0b: 800kHz 1b: 400 kHz<default at POR> |
| 0 | LOW_PTM_RIPPLE | R/W | 1b | PTM mode input voltage and current ripple reduction 0b: Disable 1b: Enable <default at POR> |
BIT |
FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | EN_CMP_LATCH | R/W | 0b |
The EN_CMP_LATCH bit, will latch the independent comparator output after it is triggered at low state. If enabled in PROCHOT profile REG0x38[6]=1 , STAT_COMP bit REG0x22[6] keep 1b after triggered until read by host and clear 0b: Independent comparator output will not latch when it is low<default at POR> 1b: Independent comparator output will latch when it is low, host can clear CMPOUT pin by toggling this EN_CMP_LATCH bit. |
| 6 | VSYS_UVP_ENZ | R/W | 0b | To disable system under voltage protection. 0b: VSYS under voltage protection is enabled <default at POR> 1b: VSYS under voltage protection is disabled |
| 5 | EN_LEARN | R/W | 0b | LEARN mode allows the battery to discharge and converter to shut off while the adapter is present . It calibrates the battery gas gauge over a complete discharge/charge cycle. When the host determines the battery voltage is below battery depletion threshold, the host switch the system back to adapter input by writing this bit back to 0b. 0b: Disable LEARN Mode <default at POR> 1b: Enable LEARN Mode |
| 4 | IADPT_GAIN | R/W | 0b | IADPT Amplifier Ratio The ratio of voltage on IADPT and voltage across ACP and ACN. 0b: 20× <default at POR> 1b: 40× |
| 3 | IBAT_GAIN | R/W | 1b | IBAT Amplifier Ratio The ratio of voltage on IBAT and voltage across SRP and SRN 0b: 8× 1b: 16× <default at POR> |
| 2 | EN_LDO | R/W | 1b | LDO Mode Enable When battery voltage is below minimum system voltage (REG0x0C()), the charger is in pre-charge with LDO mode enabled. 0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery pack internal resistor. 1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register and clamped below 384 mA (2 cell – 4 cell, 1cell VBAT<3.0V) or 2A (1cell 3.0V<VBAT<3.6V). The system is regulated by the VSYS_MIN register. <default at POR> |
| 1 | EN_IIN_DPM | R/W | 1b | IIN_DPM Enable Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM is disabled by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes LOW. 0b: IIN_DPM disabled 1b: IIN_DPM enabled <default at POR> |
| 0 | CHRG_INHIBIT | R/W | 0b | Charge Inhibit When this bit is 0, battery charging will start with valid values in the ChargeVoltage() register and the ChargeCurrent register. 0b: Enable Charge <default at POR> 1b: Inhibit Charge |