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ZHCSG48C April 2015 – March 2017

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RUY|28
- MPQF229D

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Voltage	SRN, SRP, ACN, ACP, CMSRC, VCC, BATSRC	–0.3	30	V
	PHASE	–2	30
	ACDET, SDA, SCL, LODRV, REGN, IADP, IDCHG, PMON, ILIM, ACOK, CMPIN, CMPOUT, BATPRES, TB_STAT	–0.3	7
	PROCHOT	–0.3	5.7
	BTST, HIDRV, ACDRV, BATDRV	–0.3	36
Differential voltage	BTST-PHASE, HIDRV-PHASE ACDRV-CMSRC, BATDRV-BATSRC	–0.3	7	V
Voltage	LODRV (2% duty cycle)	–4	7	V
Voltage	HIDRV (2% duty cycle)	–4	36	V
Voltage	PHASE (2% duty cycle)	–4	30	V
Voltage	REGN (5ms)	–0.3	9	V
Maximum differential voltage	SRP–SRN, ACP–ACN	–0.5	+0.5	V
Junction temperature, T_J		–40	155	°C
Storage temperature, T_stg		–55	155	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified pin. Consult Packaging Section of the data book for thermal limitations and considerations of packages.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage	SRN, SRP, ACN, ACP, CMSRC, VCC, BATSRC	0	24	V
	PHASE	–2	24
	ACDET, SDA, SCL, LODRV, REGN, IADP, IDCHG, PMON, ILIM, ACOK, CMPIN, CMPOUT, BATPRES, TB_STAT	0	6.5
	PROCHOT	–0.3	5
	BTST, HIDRV, ACDRV, BATDRV	0	30
Maximum difference	SRP–SRN, ACP–ACN	–0.4	+0.4	V
Junction temperature, T_J		–20	125	°C
Operating free-air temperature, T_A		–40	85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq24780S	UNIT
		RUY (WQFN)
		28 PINS
R_θJA	Junction-to-ambient thermal resistance	33.3	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	29.7	°C/W
R_θJB	Junction-to-board thermal resistance	6.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	6.5	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	1.3	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

4.5 V ≤ V_VCC ≤ 24 V, –40°C ≤ T_J ≤ 125°C, typical values are at T_A = 25°C, with respect to GND (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CONDITIONS
V_VCC(OP)	VCC/ACP/ACN operating voltage		4.5		24	V
CHARGE VOLTAGE REGULATION
V_{BAT(REG_RNG)}	Battery voltage		1.024		19.2	V
V_{BAT(REG_ACC)}	Charge voltage regulation accuracy	ChargeVoltage() = 0x41A0		16.8		V
		–10°C-85°C	–0.4%		0.4%
		–40°C-125°C	–0.5%		0.5%
		ChargeVoltage() = 0x3130		12.592		V
		–10°C-85°C	–0.4%		0.4%
		–40°C-125°C	–0.5%		0.5%
		ChargeVoltage() = 0x20D0		8.4		V
		–10°C-85°C	–0.4%		0.4%
		–40°C-125°C	–0.6%		0.6%
		ChargeVoltage() = 0x1060		4.192		V
		–10°C-85°C	–0.5%		0.8%
		–40°C-125°C	–0.7%		0.8%
CHARGE CURRENT REGULATION
V_{IREG(CHG_RNG)}	Charge current regulation differential voltage	V_IREG(CHG) = V_SRP– V_SRN	0		81.28	mV
I_{CHRG(REG_ACC)}	Charge current regulation accuracy (SRN > 2.8 V)	ChargeCurrent() = 0x1000		4096		mA
		ChargeCurrent() = 0x1000	–2%		2%
		ChargeCurrent() = 0x0800		2048		mA
		ChargeCurrent() = 0x0800	–3%		3%
		ChargeCurrent() = 0x0200		512		mA
		ChargeCurrent() = 0x0200	–10%		10%
		ChargeCurrent() = 0x0100		256		mA
		ChargeVoltage() = 0x20D0, 0x3031, 0x41A0	–16%		16%
		ChargeVoltage() = 0x1060	–20%		20%
		ChargeCurrent() = 0x00C0		192		mA
		ChargeCurrent() = 0x00C0	–20%		20%
		ChargeCurrent() = 0x0080		128		mA
		ChargeCurrent() = 0x0080	–30%		30%
I_LGK(SRP-SRN)	SRP and SRN leakage mismatch		–8		8	µA
DISCHARGE CURRENT REGULATION
V_{(IREG_CHG_RNG)}	Charge current regulation differential voltage	V_{IREG(IDISCHG)} = V_SRN – V_SRP	0		322.56	mV
I_{(DCHRG_REG_ACC)}	Discharge current regulation accuracy	ChargeCurrent() = 0x2000		8192		mA
		ChargeCurrent() = 0x2000	–2%		2%
		ChargeCurrent() = 0x1000		4096		mA
		ChargeCurrent() = 0x1000	–3%		3%
		ChargeCurrent() = 0x0800		2048		mA
		ChargeCurrent() = 0x0800	–5%		5%
		ChargeCurrent() = 0x0400		1024		mA
		ChargeCurrent() = 0x0400	–8%		8%
		ChargeCurrent() = 0x0400		512		mA
		ChargeCurrent() = 0x0400	–10%		10%
INPUT CURRENT REGULATION
V_{(IREG_DPM_RNG)}	Input current regulation differential voltage	V_{(IREG_DPM)} = V_(ACP) – V_(ACN)	0		80.64	mV
I_{(DPM_REG_ACC)}	Input current regulation accuracy	InputCurrent() = 0x1000		4096		mA
		InputCurrent() = 0x1000	–2%		2%
		InputCurrent() = 0x0800		2048		mA
		InputCurrent() = 0x0800	–3%		3%
		InputCurrent() = 0x0400		1024		mA
		InputCurrent() = 0x0400	–5%		5%
		InputCurrent() = 0x0200		512		mA
		InputCurrent() = 0x0200	–12%		12%
I_LGK(ACP-ARN)	ACP and ACN leakage mismatch		–5		5	µA
INPUT CURRENT SENSE AMPLIFIER
V_(IADP)	IADP output voltage		0		3.3	V
I_(IADP)	IADPT output current		0		1	mA
A_(IADP)	IADP sense amplifier gain	V_(IADP) / V_(ACP-ACN), REG0x12[4] = 0		20		V/V
V_{(IADP_ACC)}	Current sense amplifier gain accuracy	V_(ACP-ACN) = 40 mV	–2%		2%
		V_(ACP-ACN) = 20 mV	–4%		4%
		V_(ACP-ACN) ≥ 10 mV	–7%		7%
		V_(ACP-ACN) ≥ 5 mV	–20%		20%
		V_(ACP-ACN) ≥ 2.5 mV	–30%		30%
		V_(ACP-ACN) ≥ 1.5 mV	–40%		40%
V_{(IADP_CLAMP)}	IADP clamp voltage		3		3.3	V
C_(IADP)	IADP output load capacitance	With 0 to 1mA load			100	pF
DISCHARGE CURRENT SENSE AMPLIFIER
V_(IDCHG)	IDCHG output voltage		0		3.3	V
I_(IDCHG)	IDCHG output current		0		1	mA
A_(IDCHG)	Current sense amplifier gain	V_(IDCHG)/V_(SRN-SRP), REG0x12[3] = 1		16		V/V
V_{(IDCHG_ACC)}	Current sense output accuracy	V_(SRN-SRP) = 40 mV	–5%		5%
		V_(SRN-SRP) = 20 mV	–9%		9%
		V_(SRN-SRP) = 10 mV	–17%		17%
		V_(SRN-SRP) = 5 mV	–34%		34%
V_{(IDCHG_CLAMP)}	IDCHG clamp voltage		3		3.3	V
C_(IDCHG)	IDCHG output load capacitance	With 0 to 1mA load			100	pF
SYSTEM POWER SENSE AMPLIFIER
V_(PMON)	PMON output voltage		0		3.3	V
I_(PMON)	PMON output current		0		160	µA
A_(PMON)	PMON system gain	V_(PMON)/(P_IN + P_BAT, REG0x3B[9] = 1		1		µA/W
V_{PMON_ACC}	PMON Gain Accuracy (REG0x3B[9]=1)	Adapter Only with System Power = 19.5V/45W	–4%		4%
		Adapter Only with System Power = 12V/24W	–6%		6%
		Adapter Only with System Power = 5V/9W	–10%		10%
		Battery Only with System Power 11V/44W	–4.5%		4.5%
		Battery Only with System Power 7.4V/29.8W	–7%		7%
		Battery Only with System Power 3.7V/14.4W	–10%		10%
V_{PMON_CLAMP}	PMON clamp voltage		3%		3.3%	V
C_PMON	Maximum output load capacitance	With 0 to 1 mA			100	pF
REGN REGULATOR
V_{(REGN_REG)}	REGN regulator voltage	V_VCC > V_(UVLO), V_(ACDET) > V_{(wakeup_RISE)}	5.7	6	6.3	V
I_{(REGN_LIM_Charging)}	REGN current limit when in charging mode	V_(REGN) = 0 V, V_VCC > V_(UVLO), in charging mode	80	100		mA
V_LDO(DROPOUT)	REGN output voltage in dropout	V_VCC = 5 V, I_LOAD = 20 mA	4.4	4.6	4.75	V
I_{(REGN_LIM)}	REGN current limit when not in charging	V_REGN = 0 V, V_VCC > V_(UVLO), Not in charging mode	13			mA
I_{(REGN_TSHUT)}	REGN output under thermal shutdown	V_REGN = 5V	13	23		mA
C_(REGN)	REGN output capacitor	I_LOAD = 100 µA to 50 mA		2.2		μF
V_CC UNDER VOLTAGE LOCKOUT COMPARATOR
V_VCC(UVLO)	Input undervoltage rising threshold	V_CC rising	2.4	2.6	2.8	V
V_{VCC(UVLO_HYS)}	Input undervoltage falling hysteresis			200		mV
QUIESCENT CURRENT
I_BAT	Current with battery only, T_J = 0 to 85°C, I_SRN + I_SRP + I_BATSRC + I_PHASE + I_VCC + I_ACP + I_ACN	V_BAT = 16.8 V, VCC disconnected from battery, REG0x12[15] = 1			5	μA
		V_BAT = 16.8 V, VCC connected from battery, REG0x12[15] = 1		25	44
		V_BAT = 16.8 V, VCC connect to battery, BATFET on, REG0x12[15] = 0, REGN = 0 V, Comparator and PROCHOT enabled, PMON disabled, T_J = 0 to 85°C		700	800
I_AC	Adapter current, I_VCC + I_ACP + I_ACN + I_ACDRV + I_CMSRC	V_{(VCC_ULVO)} < V_VCC < V_(ACOVP), V_(ACDET) > 2.4 V, charge disabled		0.65	0.8	mA
		V_{(VCC_ULVO)} < V_VCC < V_(ACOVP), V_(ACDET) > 2.4 V, charge enabled, no switching		1.6	3
		V_{(VCC_ULVO)} < V_VCC < V_(ACOVP), V_(ACDET) > 2.4 V, charge enabled, switching, MOSFET Qg 4nC		10
ACOK COMPARATOR
V_{(ACOK_RISE)}	ACOK rising threshold	V_VCC > V_{(VCC_UVLO)}, ACDET ramps up	2.375	2.4	2.425	V
V_{(ACOK_FALL)}	ACOK falling threshold	V_VCC > V_{(VCC_UVLO)}, ACDET ramps down	2.3	2.345	2.395	V
V_{(WAKEUP_RISE)}	WAKEUP detect rising threshold	V_VCC > V_{(VCC_UVLO)}, ACDET ramps up		0.57	0.8	V
V_{(WAKEUP_FALL)}	WAKEUP detect falling threshold	V_VCC > V_{(VCC_UVLO)}, ACDET ramps down	0.3	0.51		V
VCC to SRN COMPARATOR (VCC_SRN)
V_{(VCC-SRN_FALL)}	VCC-SRN falling threshold to turn off ACFET	VCC ramps down to SRN	–20	60	140	mV
V_{(VCC-SRN _RISE)}	VCC-SRN rising threshold to turn on ACFET	VCC ramps up above SRN	170	260	360	mV
ACN to SRN COMPARATOR (ACN_SRN)
V_{(ACN-SRN_FALL)}	ACN to BAT falling threshold VCC ramps up above SRN	ACN ramps down towards SRN	120	200	280	mV
V_{(ACN- SRN _RISE)}	ACN to BAT rising threshold to turn on BATFET	ACN ramps above SRN	220	290	360	mV
HIGH SIDE IFAULT COMPARATOR (IFAULT_HI)
V_{(ACN_PH_RISE)}	ACN to PH rising threshold	reg0x37 bit [7] = 0	450	750	1200	mV
LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)
V_{(IFAULT_LO_RISE)}	PHASE to GND rising threshold	reg0x37 bit [6] = 1	180	250	340	mV
INPUT OVERVOLTAGE COMPARATOR (ACOVP)
V_(ACOV)	VCC overvoltage rising threshold	VCC ramps up	24	26	28	V
V_{(ACOV_HYS)}	VCC overvoltage falling hysteresis	VCC ramps down		1		V
INPUT OVERCURRENT COMPARATOR (ACOC)
V_(ACOC)	Rising threshold w.r.t. ICRIT input current limit	REG0x37[9] = 1	180%	200%	220%
V_{(ACOC_CLAMP)}	ACOC threshold	V_(ACP) – V_(ACN)	50		190	mV
BAT OVERVOLTAGE COMPARATOR (BAT_OVP)
V_OVP(RISE)	Overvoltage rising threshold as percentage of V_BAT(REG)	SRN ramps up	103%	104%	106%
V_OVP(FALL)	Overvoltage falling threshold as percentage of V_BAT(REG)	SRN ramps down		102%
I_OVP	Discharge resistor on SRP	VSRN > 6 V		6		mA
I_OVP	Discharge resistor on SRP	VSRN = 4.5 V		2.5		mA
CHARGE OVERCURRENT COMPARATOR (CHG_OCP)
V_OCP(limit)	Cycle-by-cycle overcurrent limit, measured voltage between SRP and SRN	ChargeCurrent() = 0x0xxxH	54	60	66	mV
		ChargeCurrent() = 0x1000H – 0x17C0H	80	90	100	mV
		ChargeCurrent() = 0x1800H – 0x1FC0H	110	120	130	mV
CHARGE UNDERCURRENT COMPARATOR (CHG_UCP)
V_UCP(FALL)	Cycle-by-cycle undercurrent falling threshold	SRP ramps down towards SRN	1	5	9	mV
LIGHT LOAD COMPARATOR (LIGHT_LOAD)
V_LL(FALL)	Light load falling threshold	SRP ramps down towards SRN		1.25		mV
V_{LL(RISE_HYST)}	Light load rising hysteresis	SRP ramps above SRN		1.25		mV
BATTERY DEPLETION COMPARATOR (BAT_DEPL)
V_{BAT(DEPL_FALL)}	Battery depletion falling threshold, as percentage of voltage regulation limit	REG0x3B[15:14] = 00	56%	60%	64%
		REG0x3B[15:14] = 01	60%	64%	68%
		REG0x3B[15:14] = 10	64%	68%	72%
		REG0x3B[15:14] = 11	68%	72%	78%
V_{BAT(DEPL_RISE_ HYST)}	Battery depletion rising hysteresis	REG0x3B[15:14] = 00	225	305	400	mV
		REG0x3B[15:14] = 01	240	325	430
		REG0x3B[15:14] = 10	255	345	450
		REG0x3B[15:14] = 11	280	370	490
V_{BAT(DEPL_RDEG)}	Battery depletion rising deglitch	Delay to turn on BATFET and turn off ACFET during LEARN cycle		600		ms
V_{BAT(DEPL_FDEG)}	Battery depletion falling deglitch	Delay to turn off BATFET and turn on ACFET during LEARN cycle		10		µs
BATTERY LOWV COMPARATOR (BAT_LOWV)
V_{BAT(LV_FALL)}	Battery LOWV falling threshold	SRN ramps down	2.3	2.5	2.8	V
V_{BAT(LV_RHYST)}	Battery LOWV rising hysteresis	SRN ramps up		200		mV
I_{BAT(LV_RESET)}	Battery LOWV charge current limit	Measure across SRP and SRN		5		mV
THERMAL SHUTDOWN COMPARATOR (TSHUT)
T_SHUT	Thermal shutdown rising temperature	Temperature ramps up		155		°C
T_SHUT(HYS)	Thermal shutdown hysteresis, falling	Temperature ramps down		20		°C
ILIM COMPARATOR
V_ILIM(FALL)	ILIM as converter enable falling threshold	V_ILIM falling	60	75	90	mV
V_ILIM(RISE)	ILIM as converter enable rising threshold	V_ILIM rising	90	105	120	mV
INDEPENDENT COMPARATOR
V_(CMPOS)	Comparator input offset		–4		4	mV
V_(CMPCM)	Comparator input common-mode		0		6.5	V
V_(CMPREF)	Comparator reference voltage (CMPIN falling)	REG0x3B[7] = 0	2.28	2.3	2.32	V
V_(CMPREF)	Comparator reference voltage (CMPIN falling)	REG0x3B[7] = 1	1.18	1.2	1.22	V
V_(CMPRISE)	Comparator reference hysteresis	REG0x3B[6] = 0		100		mV
PWM OSCILLATOR
F_SW	PWM switching frequency	REG0x12[9:8] = 00	510	600	690	kHz
		REG0x12[9:8] = 01	680	800	920
		REG0x12[9:8] = 10	850	1000	1150
BATFET GATE DRIVER (BATDRV)
I_BAT(FET)	BATDRV charge pump current limit	V_BAT(DRV) – V_BAT(SRC) = 5 V	40	60		µA
	Gate drive voltage on BATFET	V_BAT(DRV) – V_BAT(SRC) when V_(SRN) > V_BAT(UVLO)	5.5	6.1	6.8	V
R_{BAT(DRV_OFF)}	BATDRV turn-off resistance		5	6.2	7.4	kΩ
R_{BAT(DRV_LOAD)}	Minimum Load between gate and source		500			kΩ
ACFET GATE DRIVER (ACDRV)
I_(ACFET)	ACDRV charge pump current limit	V_(ACDRV) – V_(CMSRC) = 5 V	40	60		µA
	Gate drive voltage on ACFET	V_(ACDRV) – V_(CMSRC) when V_VCC > V_(UVLO)	5.5	6.1	6.8	V
R_{(ACDRV_OFF)}	ACDRV turn-off resistance		5	6.2	7.4	kΩ
R_{(ACDRV_LOAD)}	Minimum load between gate and source		500			kΩ
PWM HIGH SIDE DRIVER (HIDRV)
R_{DS(HI_ON)}	High-side driver (HSD) turn-on resistance	V_(BTST) – V_(PH) = 5.5 V		6	10	Ω
R_{DS(HI_OFF)}	High-side driver (HSD) turn-off Resistance	V_(BTST) – V_(PH) = 5.5 V		0.9	1.4	Ω
V_{(BTST_REFRESH)}	Bootstrap refresh comparator threshold voltage	V_(BTST) – V_(PH) when low side refresh pulse is requested	3.85	4.3	4.7	V
PWM LOW SIDE DRIVER (LODRV)
R_{DS(LO_ON)}	Low-side driver (LSD) turn-on resistance			7.5	12	Ω
R_{DS(LO_OFF)}	Low-side driver (LSD) turn-off resistance			0.75	1.25	Ω
INTERNAL SOFT START
I_STEP	Soft start step size			64		mA
t_STEP	Soft start step time			400		µs
PROCHOT
V_(ICRIT)	ICRIT comparator threshold	REG0x3C[15:11] = 01001, as percentage of input current limit, InputCurrent() = 0x1000	147%	150%	153%
V_(INOM)	INOM comparator threshold	as percentage of input current limit, InputCurrent()=0x0800	107%	110%	112%
V_(IDCHG)	IDCHG comparator threshold	REG0x3D[15:11] = 10000, as voltage between SRN and SRP	160	163.84	167	mV
V_(IDCHG)	IDCHG comparator threshold	REG0x3D[15:11] = 00100, as voltage between SRN and SRP	38	40.96	44	mV
V_(VSYS)	VSYS comparator threshold	REG0x3C[7:6] = 01	5.88	6	6.12	V
LOGIC INPUT (SDA, SCL, BATPRES)
V_IN(LO)	Input low threshold				0.8	V
V_IN(HI)	Input high threshold		2.1			V
V_IN(LEAK)	Input bias current	V = 7 V	–1			µA
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA, CMPOUT, TB_STAT)
V_O(LO)	Output saturation voltage	5-mA drain current			500	mV
V_O(LEAK)	Leakage current	V = 7 V	–1		1	µA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
V_{O(LEAK_PROCHOT)}	Output saturation voltage	17-mA drain current			300	mV
V_{O(LEAK_PROCHOT)}	Leakage current	V = 5.5 V	–1		1	µA

6.6 Timing Requirements

4.5 V ≤ V_VCC ≤ 24 V, –40°C ≤ T_J ≤ 125°C, typical values are at T_A = 25°C, with respect to GND (unless otherwise noted)

PARAMETER			MIN	TYP	MAX	UNIT
ACOK COMPARATOR
t_{ACOK_RISE_DEG}	ACOK rising deglitch to turn on ACFET; V_ACDET > 2.4V ^[GBD]	V_VCC > V_{VCC_UVLO}, ACDET ramps up, 1st time or REG0x12[12] = 0	100	150	200	ms
t_{ACOK_RISE_DEG}		V_VCC > V_{VCC_UVLO}, ACDET ramps up, Not 1st time or REG0x12[12] = 1	0.9	1.3	1.7	s
t_{ACOK_FALL_DEG}	ACOK falling deglitch to turn off ACFET ^[GBD]	V_VCC > V_{VCC_UVLO}, ACDET ramps down			3	µs
INPUT OVERCURRENT COMPARATOR (ACOC)
t_{ACOC_DEG}	Deglitch time to latch off ACFET		9	12	15	ms
SMBus TIMING CHARACTERISTICS
t_R	SCLK/SDATA rise time				1	µs
t_F	SCLK/SDATA fall time				300	ns
t_W(H)	SCLK pulse width high		4		50	µs
t_W(L)	SCLK pulse width low		4.7			µs
t_SU(STA)	Setup time for start condition		4.7			µs
t_H(STA)	Start condition hold time after which first clock pulse is generated		4			µs
t_SU(DAT)	Data setup time		250			ns
t_H(DAT)	Data hold time		300			ns
t_SU(STOP)	Setup time for stop condition		4			µs
t_(BUF)	Bus free time between start and stop condition		4.7			µs
F_S(CL)	Clock frequency		10		100	kHz
HOST COMMUNICATION FAILURE
t_timeout	SMBus bus release timeout⁽¹⁾		25		35	ms
t_BOOT	Deglitch for watchdog reset signal		10			ms
t_WDI	Watchdog timeout period, REG0x12 [14:13] = 01⁽²⁾		4	5	6	s
t_WDI	Watchdog timeout period, REG0x12 [14:13] = 10⁽²⁾		70	88	105
t_WDI	Watchdog timeout period, REG0x12 [14:13] = 11⁽²⁾ (default)		140	175	210
PWM DRIVER TIMING
t_{DEADTIME_RISE}	Driver dead time from low side to high side			20		ns
t_{DEADTIME_FALL}	Driver dead time from high side to low side			20		ns

(1) Devices participating in a transfer timeout when any clock low exceeds the 25-ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35-ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified because it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).

(2) User can adjust threshold through SMBus ChargeOption() REG0x12.

Figure 1. SMBus Communication Timing Waveforms

6.7 Typical Characteristics

VIN = 20 V

Figure 2. Efficiency During Charging

VIN = 5 V

Figure 4. Efficiency During Charging

VIN = 12 V

Figure 3. Efficiency During Charging

VIN = 20 V

Figure 5. Efficiency During Boost