| ACN |
1 |
Input current sense resistor negative input. Place an optional 0.01-µF ceramic capacitor from ACN to GND for common-mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential mode filtering. |
| ACP |
2 |
Input current sense resistor positive input. Place a 0.1-µF ceramic capacitor from ACP to GND for common-mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential-mode filtering. |
| CMSRC |
3 |
ACDRV charge pump source input. Place a 4-kΩ resistor from CMSRC to the common source of ACFET (Q1) and RBFET (Q2) to limit the inrush current on CMSRC pin. |
| ACDRV |
4 |
Charge pump output to drive both adapter input N-channel MOSFET (ACFET) and reverse blocking N-channel MOSFET (RBFET). ACDRV voltage is 6 V above CMSRC when ACOK is HIGH. Place a 4-kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the inrush current on ACDRV pin. |
| ACOK |
5 |
Active HIGH AC adapter detection open drain output. It is pulled HIGH to external pullup supply rail by external pullup resistor when a valid adapter is present (ACDET above 2.4 V, VCC above UVLO but below ACOV and VCC above BAT). If any of the above conditions is not valid, ACOK is pulled LOW by internal MOSFET. Connect a 10-kΩ pullup resistor from ACOK to the pullup supply rail. |
| ACDET |
6 |
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to ACDET pin to GND pin. When ACDET pin is above 0.6 V and VCC is above UVLO, REGN LDO is present, ACOK comparator, input current buffer (IADP), discharge current buffer (IDCHG), independent comparator, and power monitor buffer (PMON) can be enabled with SMBus. When ACDET is above 2.4V, and VCC is above SRN but below ACOV, ACOK goes HIGH. |
| IADP |
7 |
Buffered adapter current output. V(IADP) = 20 or 40 × (V(ACP) – V(ACN))
The ratio of 20x and 40x is selectable with SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IADP pin to GND. This pin can be floating if this output is not in use. |
| IDCHG |
8 |
Buffered discharge current. V(IDCHG) = 8 or 16 × (V(SRN) – V(SRP))
The ratio of 8x or 16x is selectable with SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IDSCHG pin to GND. This pin can be floating if this output is not in use. |
| PMON |
9 |
Buffered total system power. The output current is proportional to the total power from the adapter and battery. The ratio is selectable through SMBus. Place a resistor from PMON pin to GND to generate PMON voltage. Place a 100-pF (or less) ceramic decoupling capacitor from PMON pin to GND. This pin can be floating if this output is not in use. |
| PROCHOT |
10 |
Active low, open-drain output of the processor hot indicator. The charger IC monitors events like adapter current, battery discharge current. After any event in the PROCHOT profile is triggered, a minimum 10-ms pulse is asserted. |
| SDA |
11 |
SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. SMBus communication starts when VCC is above UVLO. Connect a 10-kΩ pullup resistor according to SMBus specifications. |
| SCL |
12 |
SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. SMBus communication starts when VCC is above UVLO. Connect a 10-kΩ pullup resistor according to SMBus specifications. |
| CMPIN |
13 |
Input of independent comparator. Internal reference, output polarity and deglitch time is selectable by SMBus. Place a resistor between CMPIN and CMPOUT to program hysteresis when the polarity is HIGH. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating. |
| CMPOUT |
14 |
Open-drain output of independent comparator. Place 10-kΩ pullup resistor from CMPOUT to pullup supply rail. Comparator reference, output polarity and deglitch time is selectable by SMBus. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating. |
| BATPRES |
15 |
Active low battery present input signal. Low indicates battery present, high indicates battery absent. The device exits the LEARN function and turns on ACFET/RBFET within 100 µs if BATPRES pin is pulled high. Upon BATPRES from LOW to HIGH, battery charging and hybrid power boost mode are disabled. The host can enable charging and hybrid power boost mode by write to REG0x14() and REG0x15() when BATPRES is HIGH |
| TB_STAT |
16 |
Active low, open-drain output for hybrid power boost mode indication. It is pulled low when the IC is operating in boost mode. Otherwise, it is pulled high. Connect a 10-kΩ pullup resistor from TB_STAT pin to the pullup supply rail. |
| BATSRC |
17 |
Connect to the source of N-channel BATFET. BATDRV voltage is 6 V above BATSRC to turn on BATFET. |
| BATDRV |
18 |
Charge pump output to drive N-channel MOSFET between battery and system (BATFET). BATDRV voltage is
6 V above BATSRC to turn on BATFET and power system from battery. BATDRV is shorted to BATSRC to turn off BATFET. Place a 4-kΩ resistor from BATDRV to the gate of BATFET limits the inrush current on BATDRV pin. |
| SRN |
19 |
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with a 0.1-µF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-µF ceramic capacitor from SRP to SRN to provide differential mode filtering. |
| SRP |
20 |
Charge current sense resistor positive input. Connect a 0.1-µF ceramic capacitor from SRP to SRN to provide differential mode filtering. |
| ILIM |
21 |
Charge current and discharge current limit.VILIM = 20 × (VSRP – VSRN) for charge current and VILIM = 5 × (VSRN – VSRP) for discharge current. Program ILIM voltage by connecting a resistor divider from system reference 3.3-V rail to ILIM pin to GND pin. The lower of ILIM voltage and 0x14() (for charge) or 0x39 (for discharge) reference sets actual regulation limit. The minimum voltage on ILIM to enable charge or discharge current regulation is 120 mV. |
| GND |
22 |
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plan through pad underneath IC. |
| LODRV |
23 |
Low-side power MOSFET driver output. Connect to low-side N-channel MOSFET gate. |
| REGN |
24 |
6-V linear regulator output supplied from VCC. The LDO is active when ACDET above 0.6 V, VCC above UVLO. Connect a ≥ 2.2-µF 0603 ceramic capacitor from REGN to GND. The diode between REGN and BTST is integrated. |
| BTST |
25 |
High-side power MOSFET driver power supply. Connect a 47-nF capacitor from BTST to PHASE. The diode between REGN and BTST is integrated inside the IC. |
| HIDRV |
26 |
High-side power MOSFET driver output. Connect to the high side N-channel MOSFET gate. |
| PHASE |
27 |
High-side power MOSFET driver source. Connect to the source of the high-side N-channel MOSFET. |
| VCC |
28 |
Input supply from adapter or battery. Use 10-Ω resistor and 1-µF capacitor to ground as a low pass filter to limit inrush current. A diode OR is connected to VCC. It powers charger IC from input adapter and battery. |
| PowerPAD™ |
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always solder the PowerPAD to the board and have vias on the PowerPAD plane connecting to analog ground and power ground planes. It also serves as a thermal pad to dissipate the heat. |