7 Pin Configuration and Functions

Figure 7-1 24-Pin VQFNRGE Package(Top View)

Figure 7-2 24-Pin VQFNRGE Package(Top View)

Table 7-1 Pin Functions

PIN		NUMBER	TYPE	DESCRIPTION
BQ24296	BQ24297	NUMBER	TYPE	DESCRIPTION
VBUS	VBUS	1,24	P	Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-μF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
PSEL	PSEL	2	I	Power source selection input. High indicates a USB host source and Low indicates an adapter source.
–	D+	2	I Analog	Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary detection in bc1.2, and non-standard adapters.
PG	–	3	O	Open drain active low power good indicator. Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA.
–	D–	3	I Analog	Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary detection in bc1.2, and non-standard adapters.
STAT	STAT	4	O	Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in the charge blinks at 1 Hz.
SCL	SCL	5	I	I²C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA	SDA	6	I/O	I²C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
INT	INT	7	O	Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active low, 256-μs pulse to host to report charger device status and fault.
OTG	OTG	8	I Digital	USB current limit selection pin during buck mode, and active high enable pin during boost mode.
				For BQ24296, when in buck mode with USB host (PSEL = High), when OTG = High, IIN limit = 500 mA and when OTG = Low, IIN limit = 100 mA. For BQ24297, when in buck mode with USB host, when OTG = High, IIN limit = 500 mA and when OTG = Low, IIN limit = 100 mA.
				The boost mode is activated when the REG01[5] = 1 and OTG pin is High.
CE	CE	9	I	Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must be pulled high or low.
ILIM	ILIM	10	I	ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from ILIM pin to ground to set the maximum limit as I_INMAX = (1V/R_ILIM) × K_ILIM. The actual input current limit is the lower one set by ILIM and by I²C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA.
TS	TS	11	I Analog	Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost disable when TS pin is out of range. A 103AT-2 thermistor is recommended.
QON	QON	12	I	BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2-ms high level turns on BATFET to exit shipping mode. It has internal 1-MΩ (Typ) pull down. For backward compatibility, when BATFET enable control function is not used, the pin can be no connect or tied to TS pin (10-kΩ NTC thermister only). (Refer to Section 9.3.1.2.2 for detail description).
BAT	BAT	13,14	P	Battery connection point to the positive pin of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10 μF closely to the BAT pin.
SYS	SYS	15,16	I	System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage.
PGND	PGND	17,18	P	Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin.
SW	SW	19,20	O	Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
BTST	BTST	21	P	PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
REGN	REGN	22	P	PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin.
PMID	PMID	23	O	Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance, connect a 1-μF capacitor on VBUS to PGND, and the recommended 8.2 μF or more on PMID to PGND.
Thermal Pad	Thermal Pad	–	P	Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter.