ZHCSAF6H October 2012 – August 2015
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Device Options
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Charge Profile
- 9.3.2 EN1 and EN2 Pins
- 9.3.3 External Settings: ISET, ILIM and VIN_DPM
- 9.3.4 BC1.2 D+/D- Detection
- 9.3.5 Transient Response
- 9.3.6 AnyBoot Battery Detection
- 9.3.7 Input Voltage Based DPM
- 9.3.8 Sleep Mode
- 9.3.9 Input Over-Voltage Protection
- 9.3.10 NTC Monitor
- 9.3.11 Production Test Mode
- 9.3.12 Safety Timer
- 9.3.13 Watchdog Timer
- 9.3.14 Fault Modes
- 9.3.15 Dynamic Power Path Management
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- RGE|24
訂購信息
7 Pin Configuration and Functions
YFF Package / RGE Package
30-Pin DSBGA / 24-Pin QFN
Top View / Top View
Pin Functions
| PIN | I/O | DESCRIPTION | ||||
|---|---|---|---|---|---|---|
| NAME | bq24251 | bq24253 | ||||
| YFF | RGE | YFF | RGE | |||
| IN | A5,B5,C5 | 19 | A5,B5,C5 | 19 | I | Input power supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to PGND with >2μF ceramic capacitor |
| PMID | D5 | 20 | D5 | 20 | I | Connection between blocking FET and high-side FET. |
| SW | A4, B4, C4 | 17–18 | A4, B4, C4 | 17–18 | O | Inductor Connection. Connect to the switching side of the external inductor. |
| BOOT | E5 | 21 | E5 | 21 | I | High Side MOSFET Gate Driver Supply. Connect a 0.033μF ceramic capacitor (voltage rating > 15V) from BOOT to SW to supply the gate drive for the high side MOSFETs. |
| PGND | A3, B3, C3, F3 | 15–16 | A3, B3, C3, F3 | 15–16 | Ground terminal. Connect to the ground plane of the circuit. | |
| SYS | A2, B2, C2 | 13–14 | A2, B2, C2 | 13–14 | I | System Voltage Sense and switched-mode power supply (SMPS) output filter connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with >20μF. |
| BAT | A1, B1, C1 | 11–12 | A1, B1, C1 | 11–12 | I/O | Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT with a >1μF capacitor. |
| TS | F1 | 9 | F1 | 9 | I | Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from LDO to GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA or PSE compatibility. See the NTC Monitor section for more details on operation and selecting the resistor values. |
| VDPM | E4 | 23 | E4 | 23 | I | Input DPM Programming Input. Connect a resistor divider between IN and GND with VDPM connected to the center tap to program the Input Voltage based Dynamic Power Management threshold (VIN_DPM). The input current is reduced to maintain the supply voltage at VIN_DPM. The reference for the regulator is 1.2V. Short pin to GND if external resistors are not desired—this sets a default of 4.68V for the input DPM threshold. |
| ISET | D1 | 10 | D1 | 10 | I | Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast charge current. The charge current is programmable from 300mA to 2A. |
| ILIM | F5 | 22 | F5 | 22 | I | Input Current Limit Programming Input. Connect a resistor from ILIM to GND to program the input current limit for IN. The current limit is programmable from 0.5A to 2A. ILIM has no effect on the USB input. If an external resistor is not desired, short to GND for a 2A default setting. |
| CE | D4 | 1 | D4 | 1 | I | Charge Enable Active-Low Input. Connect CE to a high logic level to place the battery charger in standby mode. |
| EN1 | – | – | F2 | 5 | I | Input Current Limit Configuration Inputs. Use EN1, and EN2 to control the maximum input current and enable USB compliance. See Table 1 for programming details. |
| EN2 | – | – | E2 | 6 | I | |
| CHG | – | – | E3 | 7 | O | Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains low while charging. CHG is high impedance when the charging terminates and when no supply exists. CHG does not indicate recharge cycles. |
| PG | E1 | 8 | E1 | 8 | O | Power Good Open Drain Output. PG is pulled low when a valid supply is connected to IN. A valid supply is between VBAT+VSLP and VOVP. If no supply is connected or the supply is out of this range, PG is high impedance. |
| STAT | E3 | 7 | – | – | O | Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low during charging. STAT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a 256μs pulse is sent out as an interrupt for the host. STAT is enabled/disabled using the EN_STAT bit in the control register. STAT will indicate recharge cycles. Connect STAT to a logic rail using an LED for visual indication or through a 10kΩ resistor to communicate with the host processor. |
| INT | – | – | – | – | O | Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during charging. INT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a 256μs pulse is sent out as an interrupt for the host. INT will indicate recharge cycles. Connect INT to a logic rail through a 10kΩ resistor to communicate with the host processor. |
| SCL | E2 | 6 | – | – | I | I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor. |
| SDA | F2 | 5 | – | – | I/O | I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor. |
| D+ | D3 | 2 | D3 | 2 | I | BC1.2 compatible D+/D– Based Adapter Detection. Detects DCP, SDP, and CDP. Also complies with the unconnected dead battery provision clause. D+ and D- are connected to the D+ and D– outputs of the USB port at power up. Also includes the detection of Apple™ and TomTom™ adapters where a 500mA input current limit is enabled. The PG pin will remain high impedance until the detection has completed. |
| D– | D2 | 3 | D2 | 3 | I | |
| LDO | F4 | 24 | F4 | 24 | O | LDO output. LDO is regulated to 4.9V and drives up to 50mA. Bypass LDO with a 1μF ceramic Capacitor. LDO is enabled when VUVLO < VIN <18V. |
| AGND | – | 4 | – | 4 | Analog Ground for QFN only. Connect to the thermal pad and the ground plane of the circuit. | |