1.1 Features

• 300-MHzARM926EJ-S™ RISC MPU
• ARM926EJ-S Core
• 32-Bit and 16-Bit (Thumb®) Instructions
• Single-Cycle MAC
• ARM Jazelle® Technology
• Embedded ICE-RT™ for Real-Time Debug
• ARM9™ Memory Architecture
• 16KB of Instruction Cache
• 16KB of Data Cache
• 8KB of RAM (Vector Table)
• 64KB of ROM
• Enhanced Direct Memory Access Controller 3 (EDMA3):
• 2 Channel Controllers
• 3 Transfer Controllers
• 64 Independent DMA Channels
• 16 Quick DMA Channels
• Programmable Transfer Burst Size
• 128KB of On-Chip Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
• Two External Memory Interfaces:
• EMIFA
  • NOR (8- or 16-Bit-Wide Data)
  • NAND (8- or 16-Bit-Wide Data)
  • 16-Bit SDRAM with 128-MB Address Space
• DDR2/Mobile DDR Memory Controller with one of the following:
  • 16-Bit DDR2 SDRAM with 256-MB Address Space
  • 16-Bit mDDR SDRAM with 256-MB Address Space
• Three Configurable 16550-Type UART Modules:
• With Modem Control Signals
• 16-Byte FIFO
• 16x or 13x Oversampling Option
• Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
• One Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
• One Master and Slave Inter-Integrated Circuit (I2C Bus™)
• USB 2.0 OTG Port with Integrated PHY (USB0)
• USB 2.0 High- and Full-Speed Client
• USB 2.0 High-, Full-, and Low-Speed Host
• End Point 0 (Control)
• End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):
• Transmit and Receive Clocks
• Two Clock Zones and 16 Serial Data Pins
• Supports TDM, I2S, and Similar Formats
• DIT-Capable
• FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
• IEEE 802.3 Compliant
• MII Media-Independent Interface
• RMII Reduced Media-Independent Interface
• Management Data I/O (MDIO) Module
• Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Packages:
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
• 361-Ball PBGA [ZWT Suffix], 0.80-mm Ball Pitch
• Industrial Temperature

1.2 Applications

• Medical, Healthcare, and Fitness
• Building Automation
• ePOS

1.3 Description

The AM1802 ARM microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I²C Bus) interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows® debugger interface for visibility into source code execution.

1.4 Functional Block Diagram

Figure 1-1 Functional Block Diagram