OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$?> VER=1.0Font0=Verdana,14Font1=Verdana,14,BRect0=2,0,0,85,22Rect1=1,0,0,85,10Rect2=1,0,10,10,17Rect3=1,10,10,75,17Rect4=1,75,10,85,17Rect5=1,0,17,50,22Rect6=1,50,17,85,22Text0=0,2,2,TitleText1=0,2,11,SizeText2=0,2,18,DateText3=0,12,11,Document No.Text4=0,77,11,RevText5=0,52,18,SheetText6=0,70,18,ofField0=1,T,11,2,80Field1=1,T,11,5,80Field2=1,S,4,13,5Field3=1,T,14,13,40Field4=1,R,78,13,6Field5=1,D,12,18,30Field6=1,P,64,18,3Field7=1,A,77,18,37F0=TPS7H4010-SEP Radiation Hardened 3.5-V to 32-V, 6-A=F1=Synchronous Step-Down Converter in Space Enhanced Plastic&F3=Datasheet: SNVSBL0 EVM: SNVU744F4=*F5=December 13, 2020F6=1F7=1T@T Arial#TPS7H4010-SEP Transient SimulationSymbol????333333??"@" Arial;FASTSS = 0 for normal soft-start time as determined by CSS+FASTSS = 1 decreases soft-start time by 5x7MODE = 0 for simulation that includes startup behaviornMODE = 1 for simulation that bypasses startup sequence (ensure that initial conditions are set appropriately)Symbol????333333??;T_0459B63020201213142024;88T_04598CF020201213142228;T_04597A3020201213142231?08088T_04595FF020201213142235;88T_10084D3020201213142308?80880T_100850F020201213142308;8X8XT_100854B020201213142308;88T_10088CF020201213142312?88888T_100890B020201213142312; 8  8 T_1008D7F020201213142316?88888T_1008DBB020201213142316?08 0808 T_1009322020201213142320?8 88 8 8T_100935E020201213142320;PPPPT_061D842020201213142345;@PP@PPT_06223C2020201213142348?pPppPT_0614ECE020201213142414?PPPT_0614F0A020201213142414;P0P@P0P@T_063316D020201213142656;PPPPT_0633C1F020201213142702?T_0633C5B020201213142702;PxPPxPT_0634F5A020201213142715?(PP@(P(@P@T_0624975020201213142745;P@PPP@PPT_06249B1020201213142745;((T_06256BB020201213142750;PPPPT_06256F7020201213142750;(x((x(T_06262EE020201213142753;(P(PT_062632A020201213142753;PPPPT_06285F2020201213142807?T_062A7A7020201213143612;T_062D098020201213143624?000T_062F42D020201213143635;00T_06304F7020201213143638;0000T_0630533020201213143638;00T_063E61A020201213143641;0000T_063E656020201213143641;00T_063F900020201213143644;0000T_063F93C020201213143644;00T_064140C020201213143647;00 00 T_0641448020201213143647; 0  0 T_0642E3B020201213143650;0 000 00T_0642E77020201213143650;T_06471A0020201213143758?PPPT_06471DC020201213143758;@X@XT_0648F7C020201213143802;T_06398B4020201213143815;( (( (T_0927521020201213143958?PPT_092755D020201213143958?(H(H(T_0926307020201213144005;T_0926343020201213144005;0 0 T_04AADD7020201213144533;T_04A960B020201213144535?T_04A9647020201213144535;T_04A6B27020201213144537;T_04A6B63020201213144537;T_04A5C3C020201213144544;T_04A5C78020201213144544;T_04A3A2F020201213144547;T_04A3A6B020201213144547;T_04A1B83020201213144550;T_04A1BBF020201213144550;T_049EEA3020201213144553;T_049EEDF020201213144553;    T_04C4DE2020201213144556;  T_04C4E1E020201213144556;T_04BF3E6020201213144645?xxT_04BB2E1020201213144700?0`00``T_04B20B0020201213144755;0000T_04D43E2020201213144805;@@T_04CF3FA020201213144933;T_04C957F020201213144943;@@@@T_04EBAE3020201213145122?@@@@@T_04EBB1F020201213145122;PPPPT_04E7C36020201213145208;T_04E4DBA020201213145212;PP PP T_0548F49020201213145246?P  P T_05457F6020201213145250;P P(P P(T_0545832020201213145250;T_0543F85020201213145253;T_0543FC1020201213145253;`x`xT_0538D3B020201213145432;xxxxT_0D2C78E020201213145435=xxT_0D2C7CA020201213145435EN?8( 8(( T_0D22F29020201213145451;xxxxT_15A604A020201213145532;xxT_15A6086020201213145532;T_15987A4020201213145608;T_15987E0020201213145608?T_15BDBDC020201213145611?T_15BDC18020201213145611?(((T_0A59C8C020201213153934;PPPPT_0A8CB5B020201213154021;T_0A85D7E020201213154058;xxT_0A85DBA020201213154058?P`PP`T_0A82008020201213154142;XXXXT_0A9DD3D020201213154311;XhXhT_0A9DD79020201213154311:BYp0]U1T_0F3FE0E020201213135229 TPS7H4010_TRANSTPS7H4010_TRANS[C:\Users\A0487031\AppData\Local\Temp\DesignSoft\{Tina9-TI-12172019-103356}\TPS7H4010_TRANSSCK#MODE=0 FASTSS=1TPS7H4010_TRANSLabel}}wod*FBS7H4010_TRANS ` @d*NC_00.5,1,0)2_S @d*NC_1)<0.5&V(CH)> @d*ENABLETHRESH)|V# @d*BIAS0.5|V(OUT)>0 @ @d*CBOOTVTHRESH)&V(  @d*DAP_1VTHRESH)|V#  @d*NC_20VTHRESH)|V( @d*NC_7(VTHRESH)|V( @d*PGND_0  @d*PGND_1  @d*NC_6_2 @d*NC_3 U2_S @d*NC_4VTHRESH),(VS @d*NC_5VTHRESH),-5, @d*AGNDRKHRESH),-5,  @d*SS_TRKTHRESH)&V#  @d*SW_0)>V(INM1),(V  @d*SW_1>V(INM),(VDD  @d*RT_3VTHRESH),(VS 0 @d*PGND_2HRESH),-V(  @d*PGND_3 YINT 0 V  @d*PGOOD0HRESH),-V(  @d*SW_2)>V(INM2),(V  @d*VIN_01 D IS=1E- @d*VIN_1VTHRESH),(V @d*VIN_22)>(VTHRESH @d*VCCS(VTHRESH),V(  @d*SW_3LE YINT 0 V  @d*SW_4  @d*SYNCVTHRESH),-5, P @fxg*TPS7H4010_TRANSArial333333?aR@aR@'* PSpice Model Editor - Version 17.4.0*$ * TPS7H4010N*****************************************************************************v* (C) Copyright 2017 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedH** or implied, with respect to this model, including the warranties of F** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************>** Released by: WEBENCH Design Center, Texas Instruments Inc.* Part: TPS7H4010-SEP* Date: 13DEC2020* Model Type: TRANSIENT * Simulator: TINA-TI'* Simulator Version: 9.3.200.277 SF-TI!* EVM Order Number: TPS7H4010EVM** EVM Users Guide: SNVU744 - October 2020%* Datasheet: SNVSBL0 - November 2020!* Topologies Supported: BUCK,IBB* Model Version: Final 1.00*N****************************************************************************** * Updates:* * Final 1.00* Release to Web.*N******************************************************************************* Model Usage Notes:*.* 1. The following features have been modeled/* a. Frequency foldback during soft-start* b. Current foldback * c. Current limit, Hiccup* d. IBB compatible* e. PGOOD functionalitya* 2. The operating quiescent current and thermal shutdown characteristics have not been modeled.*N*****************************************************************************s.SUBCKT TPS7H4010_TRANS AGND BIAS CBOOT DAP ENABLE FB NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 PGND_0 PGND_1 PGND_2g+ PGND_3 PGOOD RT SS_TRK SW_0 SW_1 SW_2 SW_3 SW_4 SYNC VCC VIN_0 VIN_1 VIN_2 PARAMS: MODE=0 FASTSS=1 R_R17 PGND PGND_0 1m LX_U7_U621 VIN_1 BIAS U7_BIAS_OK U7_N16735566 MUX2_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=0.5LX_U7_U615 VCC U7_N16735320 U7_N16735276 U7_VCC_OK COMPHYS_BASIC_GEN#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5JX_U7_U614 EN U7_N16735086 U7_N16735008 U7_EN_OK COMPHYS_BASIC_GEN#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.50.5, 7+ IF(V(U7_N16735566)>3.15,3.15,V(U7_N16735566)),0) }%V_U7_V13 U7_N16760362 0 1.15$V_U7_V9 U7_N16735320 0 3.14%V_U7_V7 U7_N16735086 0 1.196%V_U7_V14 U7_N16760414 0 0.85IX_U7_U618 U7_VCC_OK U7_VCCOK_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3GX_U7_U617 U7_EN_OK U7_ENOK_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3"V_U7_V12 U7_N16735188 0 +PULSE {1-MODE} 0 1u 1n 1n 1 2NX_U7_U620 BIAS U7_N16735430 U7_N16735502 U7_BIAS_OK COMPHYS_BASIC_GEN#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5$V_U7_V10 U7_N16735430 0 3.2$V_U7_V6 U7_N16735008 0 100m$V_U7_V11 U7_N16735502 0 0.1#V_U7_V8 U7_N16735276 0 0.5CX_U7_U622 U7_ENOK_B U7_ENOK_B U7_VCCOK_B U7_N16735188 SDWN4+ OR4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3OX_U7_U623 EN U7_N16760362 U7_N16760414 U7_ENABLE_VCC COMPHYS_BASIC_GEN#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5%V_U1_V14 U1_N16747077 0 1.35PX_U1_U679 U1_TOFFTIMERINPUT U1_N16750859 TOFFBAR COMP_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=0.5C_U1_C7 0 FBI .7p LE_U1_ABM1 U1_N16755741 0 VALUE { LIMIT((V(VREF) * 4.05),3.3,0) }%D_U1_D13 U1_VCOMP U1_5V D_D MX_U1_F1 U1_5V U1_N16752851 U1_TOFFTIMERINPUT 0 ERROR_AMPLIFIER_mod_U1_F1 .E_U1_E2 U1_N16745950 0 U1_VCOMP 0 0.9&C_U1_C4 0 U1_N16746537 .4p IG_U1_ABM2I1 U1_5V U1_VCOMP VALUE { LIMIT((V(VREF) - V(FBI))*33u,+ -3u,3u) }0I_U1_I1 U1_5V U1_TOFFTIMERINPUT DC 1u $V_U1_V12 U1_N16750859 0 0.9@X_U1_S1 U1_N16753555 0 U1_VCOMP 0 ERROR_AMPLIFIER_mod_U1_S1 2R_U1_R2 U1_N16746735 U1_N16746537 397k PX_U1_U681 COMP U1_N16755176 COMP_OCP COMP_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5(E_U1_E3 COMP 0 U1_N16746537 0 1/V_U1_V9 U1_N16745950 U1_N16746735 612m%C_U1_C5 U1_N16750089 0 2p KG_U1_ABM2I3 U1_N16752851 U1_VCOMP VALUE { LIMIT((V(U1_N16747345) -+ V(COMP))*35m, 0,20u) }%V_U1_V15 U1_N16755176 0 1.38DX_U1_S2 U1_N16750466 0 U1_N16750089 0 ERROR_AMPLIFIER_mod_U1_S2 .R_U1_R5 U1_N16751639 U1_VCOMP 500k OX_U1_U680 HICCUP HICCUP U1_N16753555 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3NG_U1_ABM2I2 U1_VCOMP 0 VALUE { LIMIT((V(COMP) - V(U1_N16747077))*35m,+ 0,50u) }!D_U1_D14 0 U1_VCOMP D_D V_U1_V11 U1_5V 0 10)C_U1_C6 0 U1_N16751639 31.85p NG_U1_ABM2I4 U1_VCOMP 0 VALUE { LIMIT((V(COMP) - V(U1_N16755741))*35m,+ 0,30u) }7R_U1_R3 U1_N16750089 U1_TOFFTIMERINPUT 990k .D_U1_D11 U1_TOFFTIMERINPUT U1_5V D_D %R_U1_R4 0 U1_N16750089 1G %V_U1_V10 U1_N16747345 0 150m*D_U1_D10 0 U1_TOFFTIMERINPUT D_D R_U1_R6 FBI FBI 200k NX_U1_U678 CONT RMPOK U1_N16750466 NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3 R_R18 PGND PGND_1 1m E_E1 FBI 0 FB AGND 1PX_U5_U611 U5_N16864724 U5_H_END INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5 DELAY=5uNX_U5_U626 U5_N16873419 U5_N16873419 U5_HICCUP_N PGOOD_EN U5_N168154545+ AND4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3EX_U5_U153 U5_N16875012 U5_N16873419 one_shot PARAMS: T=20 !V_U5_V5 U5_N16873139 0 +PWL 0 1 100u 1 101u 0 NX_U5_U607 U5_N16777841 U5_N16777837 INV_DELAY_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=0.5 DELAY=10u)R_U5_R8 U5_N16777841 HICCUP 1 PX_U5_U608 U5_N16777841 U5_N16777837 U5_N16777926 AND2_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=500E-3!V_U5_V4 U5_N16778004 0 1+C_U5_C7 0 U5_N16778000 4.8u IC=0 3G_U5_G3 0 U5_N16777880 U5_N16815454 0 100mOX_U5_U628 U5_N16875006 PH1 U5_N16875012 N16875009 srlatchrhp_basic_gen#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 1,1,0)} }MX_U5_U629 UVP TOFF_TIMEOUT U5_N16875006 AND2_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=500E-3#V_U5_V2 U5_N16777884 0 128%C_U5_C5 0 U5_N16777841 1n PX_U5_U612 U5_N16778000 U5_N16778004 U5_N16777947 COMP_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=0.5/R_U5_R5 U5_N16777952 U5_N16777947 1 8X_U5_S3 U5_N16777933 0 U5_N16777880 0 HICCUP1_U5_S3 OX_U5_U30 U5_N16777867 U5_H_END HICCUP U5_HICCUP_N srlatchrhp_basic_gen#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5)C_U5_C6 0 U5_N16777880 2n IC=0 %C_U5_C8 0 U5_N16777952 1n FX_U5_U627 U5_N16792752 U5_N16873139 U5_N16777926 U5_N167779334+ OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3AX_U10_U619 U10_N16817296 FBI U10_N16817256 U10_N168192345+ COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5JX_U10_U617 HICCUP U10_N16818724 INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3%V_U10_V6 U10_N16817256 0 15mPX_U10_U625 SS_DONE U10_N16819234 UVP AND2_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3LE_U10_ABM6 PGOOD_EN 0 VALUE { if ( V(U10_TDELAY) > 0.5 , 1, 0) }KX_U10_U621 U10_N16818724 U10_N16818947 U10_HICC_RES AND2_BASIC_GEN&+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3&C_U10_C161 0 U10_TDELAY 1n 9X_U10_S20 U10_N16799779 0 U10_TDELAY 0 PGOOD_U10_S20 KX_U10_U622 U10_N16818724 U10_N16818942 INV_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=500E-3&V_U10_V2 U10_N16787180 0 900m1R_U10_R285 U10_TONMIN U10_TDELAY 100k JE_U10_ABM3 U10_PG 0 VALUE { IF( V(PGOODDEL) > 0.5 | {MODE}>0.5, + V(U10_GLITCH),1 ) }%V_U10_V3 U10_N16627165 0 1.1$V_U10_V7 U10_N16817296 0 .45X_U10_S19 PGOOD_EN AGND PGOOD AGND PGOOD_U10_S19 OX_U10_U614 U10_N16627165 FBI U10_N16626981 U10_OVP_N COMPHYS_BASIC_GEN#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5CX_U10_U623 U10_OVP_N OVP INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3%V_U10_V1 U10_N16625533 0 10mLX_U10_U1_U827 U10_U1_N00420 0 U10_U1_PULSEHI AND2_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=500E-3,C_U10_U1_C178 0 U10_U1_N02680 1n ,C_U10_U1_C177 0 U10_U1_N00242 1n JX_U10_U1_U825 U10_U1_PULSEHI U10_U1_N00242 0 N00452 OR3_BASIC_GEN&+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-32R_U10_U1_R286 U10_PG U10_U1_N02680 36k NX_U10_U1_U826 0 U10_U1_N00420 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5 DELAY=50n8D_U10_U1_D10 U10_U1_PULSEHI U10_U1_N00242 D_D1 CR_U10_U1_R285 U10_U1_PULSEHI U10_U1_N00242 28.86002886k KX_U10_U1_U828 U10_U1_N02680 U10_TONMIN BUF_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=0.5#V_U10_V5 U10_N16805765 0 12, 1, 0), If(V(U3_N16775006)>0.4, 1, 0)) }6G_U3_G2 U3_1V U3_N33130 U3_N16782644 0 0.133m?X_U3_S3 U3_N16792835 0 U3_N16792801 0 Oscillator_mod_U3_S3 CX_U3_U143 U3_SYNC_INT U3_CLK_SYNC one_shot PARAMS: T=30 LE_U3_ABM7 U3_N16782644 0 VALUE { if(V(U3_N16797210) <0.701m, 13.4m,@+ if(V(U3_N16797210) > 58.17m, 58.17m, V(U3_N16797210))) }FX_U3_S28 U3_N16757802 0 U3_N16757548 ISLOPE Oscillator_mod_U3_S28 2G_U3_G3 0 U3_N16792801 U3_N16792773 0 10m"V_U3_V7 U3_N16868915 0 21 R_R13 SW SW_1 0.001m R_R19 VIN_1 VIN_2 1m R_R8 PGND PGND_3 1m .C_U6_C180 U6_VOFFSET 0 4.5p TC=0,0 'D_U6_D16 U6_HSRAMP U6_V5 D_D1 LE_U6_ABM5 U6_N16759172 0 VALUE { LIMIT(V(ISLOPE)*0.30629, 0,1) }!V_U6_V3 U6_N16758010 0 1OX_U6_U825 U6_N16734139 U6_N16734133 U6_PH1_1 PH1 OR3_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=500E-3?G_U6_ABMII4 U6_N16740446 0 VALUE { if( V(SDWN)< 0 .5 &I+ V(U6_FPWM_GATE_B) >0.5, LIMIT((V(U6_VOFFSET))* 8.904m, 0 ,20),0) }MX_U6_U829 U6_PH2_1 U6_PREBIAS PH2 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3OG_U6_ABMII1 0 U6_N16740446 VALUE { if( V(SDWN)< 0 .5, LIMIT(V(ISLOPE)*+ 3.2211m, 0 ,10),0) }4R_U6_R276 U6_N16734139 U6_N16734133 72.2 V_U6_V2 U6_V5 0 5FX_U6_U838 SDWN U6_N16756335 INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3>G_U6_ABMII2 U6_N16740446 0 VALUE { if( V(SDWN)< 0 .5,/+ LIMIT((V(COMP)-.15)* 8.904m, 0 ,20),0) }LX_U6_U844 U6_GT_PK U6_HS_TIMEOUT U6_N16734815 OR2_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=500E-3PX_U6_U826 U6_PH1_1 U6_N16734677 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5 DELAY=15n;E_U6_E2 U6_N16759176 U6_N16759068 U6_N16759172 0 1PX_U6_U841 U6_N16757793 CONT U6_HS_ON U6_N16757789 OR3_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=500E-3LG_U6_ABMII3 U6_V5 U6_HSRAMP VALUE { if(V(SDWN) <0.5, 0.519u,0) })R_U6_R278 U6_HS_CMD VIN_1 51k 1D_U6_D10 U6_N16734139 U6_N16734133 D_D1 'V_U6_V4 U6_N16759068 0 0.14606HX_U6_U839 U6_SET CLK U6_HS_ON OR2_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3(R_U6_R279 0 U6_N16759708 1e9 !V_U6_V1 U6_N16756364 0 1CX_U6_S5 U6_PH1_1B 0 U6_VOFFSET U6_N16759708 GmIphase_mod_U6_S5 GE_U6_ABM1 U6_VOFFSET_NOSAM 0 VALUE { LIMIT( (V(U6_N16759176) $+ -V(U6_N16758916) )*0.9, 0, 2) }&C_U6_C178 0 U6_HSRAMP 3.3p 0C_U6_C179 U6_N16759708 0 .45p TC=0,0 MX_U6_U846 FPWM_GATE U6_FPWM_GATE_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3OX_U6_U843 U6_HS_TIMEOUT U6_N16757793 BUF_DELAY_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=0.5 DELAY=50nKX_U6_U612 VREF FBI U6_N16734995 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5KX_U6_U835 U6_HS_CMD SW U6_HS_COMP_OUT COMP_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=0.5-R_U6_R4 U6_N16734257 0 1Meg TC=0,0 PX_U6_U629 U6_HS_ON U6_N16734815 U6_PH1_1 U6_PH1_1B srlatchrhp_basic_gen#+ PARAMS: VDD=1 VSS=0 VTHRESH=0.50.5, 0.275, 0.1m) + }.X_U4_S1 HDRV SW VIN_1 SW Driver_mod_U4_S1 MX_U4_U681 U4_N16800893 PH1 TOFF_TIMEOUT AND2_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=500E-36X_U4_S4 U4_HDRV_INT 0 CBOOT HDRV Driver_mod_U4_S4 MX_U4_U664 FPWM_GATE U4_ZX_NEG_VY U4_N16800029 AND2_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=500E-3IE_U4_ABM174 U4_N16799808 0 VALUE { LIMIT(V(U4_N16799768)*0.4452,+ 10,-10) },X_U4_S2 LDRV 0 SW PGND Driver_mod_U4_S2 BX_U4_U643 U4_LDRV_INT U4_LDRV_INTB PH2 U4_S1 U4_ZCDLRES 09+ dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-31E_U4_E3 U4_N16799810 0 U4_N16799808 0 -1LX_U4_U652 U4_LDRV_INT U4_N16800275 U4_N16800387 LDRV AND3_BASIC_GEN&+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3KX_U4_U617 U4_SWIN U4_N16799615 U4_ZCD COMP_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=0.5FX_U4_U678 FFWD U4_N16800038 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5KX_U4_U659 U4_SWIN U4_N16799810 U4_N16799878 COMP_BASIC_GEN PARAMS:+ VDD=1 VSS=0 VTHRESH=0.5NX_U4_U615 U4_ZCD U4_L_BLNCK U4_ZX_NEG_VY AND2_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=500E-3V_U4_V5 U4_S1 0 1LX_U4_U610 U4_N16800531 PH1 U4_HDRV_INT AND2_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=500E-3)D_U4_D65 PGND U4_N16799955 D_D1 OX_U4_U680 U4_LS_READY PH1 CONT U4_CONTBAR srlatchrhp_basic_gen PARAMS:+ VDD=1 VSS=0 VTHRESH=0.5ME_U4_ABM172 U4_N16800108 0 VALUE { IF(((V(SDWN) < 0.5) &((V(CBOOT) -+ V(SW)) > 2.8)), 0 , 1) }FX_U4_U651 SDWN U4_N16800387 INV_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-3-C_U4_C14 0 U4_N16800531 1n TC=0,0 -C_U4_C13 0 U4_BOOT_UVLO 1n TC=0,0 0E_U4_E1 U4_N16799615 0 U4_ZCDTHRESH 0 1PX_U4_U660 U4_N16799878 U4_L_BLNCK U4_VY_OK AND2_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=500E-37X_U4_S35 LDRV 0 U4_N16800365 VCC Driver_mod_U4_S35 R_R22 SW SW_2 0.001m MX_U2_U4 VREF U2_N16727106 SS_DONE COMP_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=0.5#V_U2_V8 U2_N16736482 0 1.1IE_U2_ABM8 U2_N16702433 0 VALUE { if( V(U2_N16732884) >0.5, 1, + MIN(V(U2_SS_INT) + ,V(U2_N16728809) )) }GX_U2_U3 SDWN HICCUP U2_DISCH OR2_BASIC_GEN PARAMS: VDD=1 VSS=0+ VTHRESH=500E-34X_U2_S2 U2_DISCH 0 SS_TRK AGND SOFT_START_U2_S2 $V_U2_V5 U2_N16727106 0 0.95#V_U2_V1 U2_N16645820 0 1.2MG_U2_ABMII2 U2_N16728282 SS_TRK VALUE { IF(V(U2_DISCH) > 0.5,0, {2u*+ (1+ 4*FASTSS))} }PG_U2_ABMII1 U2_N16645820 U2_SS_INT VALUE { IF(V(U2_DISCH) > 0.5,0, {2u*+ (1+ 4*FASTSS))} }.C_U2_C3 SS_TRK AGND 10p IC={MODE*1} 4X_U2_S1 U2_DISCH 0 U2_SS_INT 0 SOFT_START_U2_S1 -E_U2_E2 U2_N16728809 0 SS_TRK AGND 1!V_U2_V7 U2_N16732884 0 "+PWL 0 {MODE} 10u {MODE} 10.1u 0 ,C_U2_C1 U2_SS_INT 0 10n IC={MODE} FE_U2_ABM9 U2_N16733572 0 VALUE { MIN(V(U2_N16702433) ,1) }.D_U2_D62 U2_SS_INT U2_N16645820 D_D1 +D_U2_D66 SS_TRK U2_N16728282 D_D1 PX_U2_U5 U2_N16702433 U2_N16736482 PGOODDEL COMP_BASIC_GEN PARAMS: VDD=1+ VSS=0 VTHRESH=0.5&V_U2_V6 U2_N16728282 AGND 1.2(E_U2_E1 VREF 0 U2_N16733572 0 1 R_R23 SW SW_4 0.001m .ENDS TPS7H4010_TRANS*$,.subckt ERROR_AMPLIFIER_mod_U1_F1 1 2 3 4 F_U1_F1 3 4 VF_U1_F1 6VF_U1_F1 1 2 0V .ends ERROR_AMPLIFIER_mod_U1_F1*$,.subckt ERROR_AMPLIFIER_mod_U1_S1 1 2 3 4 S_U1_S1 3 4 1 2 _U1_S1RS_U1_S1 1 2 1GF.MODEL _U1_S1 VSWITCH Roff=1000e6 Ron=3k Voff=0.25V Von=0.75V .ends ERROR_AMPLIFIER_mod_U1_S1*$,.subckt ERROR_AMPLIFIER_mod_U1_S2 1 2 3 4 S_U1_S2 3 4 1 2 _U1_S2RS_U1_S2 1 2 1GD.MODEL _U1_S2 VSWITCH Roff=1e9 Ron=10m Voff=0.25V Von=0.75V .ends ERROR_AMPLIFIER_mod_U1_S2*$ .subckt HICCUP1_U5_S4 1 2 3 4 S_U5_S4 3 4 1 2 _U5_S4RS_U5_S4 1 2 1G@.MODEL _U5_S4 VSWITCH Roff=1e6 Ron=1m Voff=0.25 Von=0.8.ends HICCUP1_U5_S4*$ .subckt HICCUP1_U5_S3 1 2 3 4 S_U5_S3 3 4 1 2 _U5_S3RS_U5_S3 1 2 1GC.MODEL _U5_S3 VSWITCH Roff=1e11 Ron=1.0 Voff=0.25 Von=0.75.ends HICCUP1_U5_S3*$ .subckt PGOOD_U10_S20 1 2 3 4 #S_U10_S20 3 4 1 2 _U10_S20RS_U10_S20 1 2 1GC.MODEL _U10_S20 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8.ends PGOOD_U10_S20*$ .subckt PGOOD_U10_S19 1 2 3 4 #S_U10_S19 3 4 1 2 _U10_S19RS_U10_S19 1 2 1GC.MODEL _U10_S19 VSWITCH Roff=100e6 Ron=40 Voff=0.2 Von=0.8.ends PGOOD_U10_S19*$ .subckt PGOOD_U10_S21 1 2 3 4 #S_U10_S21 3 4 1 2 _U10_S21RS_U10_S21 1 2 1GC.MODEL _U10_S21 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8.ends PGOOD_U10_S21*$(.subckt Oscillator_mod_U3_S30 1 2 3 4 !S_U3_S30 3 4 1 2 _U3_S30RS_U3_S30 1 2 1GD.MODEL _U3_S30 VSWITCH Roff=1e9 Ron=1m Voff=0.25V Von=0.75V.ends Oscillator_mod_U3_S30*$(.subckt Oscillator_mod_U3_S26 1 2 3 4 !S_U3_S26 3 4 1 2 _U3_S26RS_U3_S26 1 2 1G@.MODEL _U3_S26 VSWITCH Roff=1e9 Ron=1m Voff=0.2 Von=0.8.ends Oscillator_mod_U3_S26*$'.subckt Oscillator_mod_U3_H1 1 2 3 4 "H_U3_H1 3 4 VH_U3_H1 1000VH_U3_H1 1 2 0V.ends Oscillator_mod_U3_H1*$(.subckt Oscillator_mod_U3_S29 1 2 3 4 !S_U3_S29 3 4 1 2 _U3_S29RS_U3_S29 1 2 1G@.MODEL _U3_S29 VSWITCH Roff=1e9 Ron=1m Voff=0.2 Von=0.8.ends Oscillator_mod_U3_S29*$'.subckt Oscillator_mod_U3_S3 1 2 3 4 S_U3_S3 3 4 1 2 _U3_S3RS_U3_S3 1 2 1GC.MODEL _U3_S3 VSWITCH Roff=1e11 Ron=1.0 Voff=0.25 Von=0.75.ends Oscillator_mod_U3_S3*$(.subckt Oscillator_mod_U3_S28 1 2 3 4 !S_U3_S28 3 4 1 2 _U3_S28RS_U3_S28 1 2 1GD.MODEL _U3_S28 VSWITCH Roff=1e9 Ron=1m Voff=0.25V Von=0.75V.ends Oscillator_mod_U3_S28*$%.subckt GmIphase_mod_U6_S5 1 2 3 4 S_U6_S5 3 4 1 2 _U6_S5RS_U6_S5 1 2 1G@.MODEL _U6_S5 VSWITCH Roff=2e9 Ron=10k Voff=.25 Von=.75.ends GmIphase_mod_U6_S5*$%.subckt GmIphase_mod_U6_S1 1 2 3 4 S_U6_S1 3 4 1 2 _U6_S1RS_U6_S1 1 2 1GC.MODEL _U6_S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25V Von=.75V.ends GmIphase_mod_U6_S1*$%.subckt GmIphase_mod_U6_F1 1 2 3 4 F_U6_F1 3 4 VF_U6_F1 1mVF_U6_F1 1 2 0V.ends GmIphase_mod_U6_F1*$%.subckt GmIphase_mod_U6_S6 1 2 3 4 S_U6_S6 3 4 1 2 _U6_S6RS_U6_S6 1 2 1G?.MODEL _U6_S6 VSWITCH Roff=2e9 Ron=1k Voff=.25 Von=.75.ends GmIphase_mod_U6_S6*$#.subckt Driver_mod_U4_S5 1 2 3 4 S_U4_S5 3 4 1 2 _U4_S5RS_U4_S5 1 2 1G>.MODEL _U4_S5 VSWITCH Roff=1e6 Ron=2 Voff=0.2 Von=0.8.ends Driver_mod_U4_S5*$#.subckt Driver_mod_U4_S1 1 2 3 4 S_U4_S1 3 4 1 2 _U4_S1RS_U4_S1 1 2 1G@.MODEL _U4_S1 VSWITCH Roff=1e9 Ron=50m Voff=0.2 Von=0.5.ends Driver_mod_U4_S1*$#.subckt Driver_mod_U4_S4 1 2 3 4 S_U4_S4 3 4 1 2 _U4_S4RS_U4_S4 1 2 1G>.MODEL _U4_S4 VSWITCH Roff=1e6 Ron=2 Voff=0.2 Von=0.8.ends Driver_mod_U4_S4*$#.subckt Driver_mod_U4_S2 1 2 3 4 S_U4_S2 3 4 1 2 _U4_S2RS_U4_S2 1 2 1G@.MODEL _U4_S2 VSWITCH Roff=1e9 Ron=50m Voff=0.2 Von=0.5.ends Driver_mod_U4_S2*$$.subckt Driver_mod_U4_S35 1 2 3 4 !S_U4_S35 3 4 1 2 _U4_S35RS_U4_S35 1 2 1G@.MODEL _U4_S35 VSWITCH Roff=10e6 Ron=1 Voff=0.2 Von=0.8.ends Driver_mod_U4_S35*$#.subckt SOFT_START_U2_S2 1 2 3 4 S_U2_S2 3 4 1 2 _U2_S2RS_U2_S2 1 2 1G?.MODEL _U2_S2 VSWITCH Roff=1e9 Ron=3k Voff=0.2 Von=0.5.ends SOFT_START_U2_S2*$#.subckt SOFT_START_U2_S1 1 2 3 4 S_U2_S1 3 4 1 2 _U2_S1RS_U2_S1 1 2 1G?.MODEL _U2_S1 VSWITCH Roff=1e9 Ron=3k Voff=0.2 Von=0.5.ends SOFT_START_U2_S1*$ .model D_D d + is=1e-015 + n=0.001 + tt=1e-011 + rs=0.05*$.subckt one_shot in out+ params: t=100 s_s1 meas 0 reset2 0 s1Ae_abm1 ch 0 value { if( v(in)>0.5 | v(out)>0.5,1,0) }!r_r2 reset2 reset 0.1 Ce_abm3 out 0 value { if( v(meas)<0.5 & v(ch)>0.5,1,0) }r_r1 meas ch {t} !c_c2 0 reset2 1.4427n c_c1 0 meas 1.4427n 6e_abm2 reset 0 value { if(v(ch)<0.5,1,0) }.model s1 vswitch+ roff=1e+009+ ron=1 + voff=0.25 + von=0.75.ends one_shot*$G.subckt srlatchrhp_basic_gen s r q qb params: vdd=1 vss=0 vthresh=0.5 Dgq 0 qint value = {if(v(r) > {vthresh},-5,if(v(s)>{vthresh},5, 0))}cqint qint 0 1nrqint qint 0 1000megd_d10 qint my5 d_d1v1 my5 0 {vdd}d_d11 myvss qint d_d1v2 myvss 0 {vss} eq qqq 0 qint 0 1Ix3 qqq qqqd1 buf_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}rqq qqqd1 q 17eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}rqb qbr qb 1 cdummy1 q 0 1n cdummy2 qb 0 1n.ic v(qint) {vss}.model d_d1 d + is=1e-015 + tt=1e-011 + rs=0.005+ n=0.1.ends srlatchrhp_basic_gen*$.model D_D1 d + is=1e-015 + tt=1e-011 + rs=0.05+ n=0.1*$K.subckt dffsr_rhpbasic_gen q qb clk d r s params: vdd=1 vss=0 vthresh=0.5 Kx1 clk clkdel1 inv_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}!r_clk clkdel1 clkdel 21.64502165c_clk clkdel 0 1nIx2 clk clkdel clkint and2_basic_gen params: vdd={vdd} vss={vss} vthresh=+ {vthresh} Ogq 0 qint value = {if(v(r) > {vthresh},-5,if(v(s) > {vthresh},5, if(v(clkint)>+ {vthresh}, !+ if(v(d)> {vthresh},5,-5),0)))}cqint qint 0 1nd_d10 qint my5 d_d1v1 my5 0 {vdd}d_d11 myvss qint d_d1v2 myvss 0 {vss} eq qqq 0 qint 0 1Ox3 qqq qqqd1 buf_delay_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}+ delay = 1nrqq qqqd1 q 17eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}rqb qbr qb 1 cdummy1 q 0 1nf cdummy2 qb 0 1nf .ic v(qint) {vss}.model d_d1 d + is=1e-015 + tt=1e-011 + rs=0.05+ n=0.1.ends dffsr_rhpbasic_gen*$@.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 1E_ABMGATE YINT 0 VALUE {{IF(V(S) > {VTHRESH}, + V(B),V(A))}}RINT YINT Y 1 CINT Y 0 1n.ENDS MUX2_BASIC_GEN*$K.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 EIN INP1 INM1 INP INM 1 9EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }8EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) } R1 OUT 1 1 C1 1 0 5nRINP1 INP1 0 1K.ENDS COMPHYS_BASIC_GEN*$<.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 3E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VSS},{VDD})}}RINT YINT Y 1 CINT Y 0 1n.ENDS INV_BASIC_GEN*$A.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} |+ V(C) > {VTHRESH} |"+ V(D) > {VTHRESH},{VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS OR4_BASIC_GEN*$B.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 "E_ABM Yint 0 VALUE {IF (V(INP) > + V(INM), {VDD},{VSS})} R1 Yint Y 1 C1 Y 0 1n.ENDS COMP_BASIC_GEN*$=.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | "+ V(B) > {VTHRESH},{VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS OR2_BASIC_GEN*$?.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & "+ V(B) > {VTHRESH},{VSS},{VDD})}}RINT YINT Y 1 CINT Y 0 1n.ENDS NAND2_BASIC_GEN*$N.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 5E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}}RINT YINT1 YINT2 1CINT YINT2 0 {DELAY*1.3}9E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VSS},{VDD})}}RINT2 YINT3 Y 1 CINT2 Y 0 1n.ENDS INV_DELAY_BASIC_GEN*$B.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} &+ V(C) > {VTHRESH} &"+ V(D) > {VTHRESH},{VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS AND4_BASIC_GEN*$>.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & "+ V(B) > {VTHRESH},{VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS AND2_BASIC_GEN*$?.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} |"+ V(C) > {VTHRESH},{VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS OR3_BASIC_GEN*$<.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 3E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS BUF_BASIC_GEN*$>.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | "+ V(B) > {VTHRESH},{VSS},{VDD})}}RINT YINT Y 1 CINT Y 0 1n.ENDS NOR2_BASIC_GEN*$L.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 + T=10EIN INP1 INM1 INP INM 1 BEHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }8EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) } R1 OUT 1 1C1 1 0 {T*1e-9}RINP1 INP1 0 10KRINM2 INM2 0 10K.ENDS COMPHYS2_BASIC_GEN*$N.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 5E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}}RINT YINT1 YINT2 1CINT YINT2 0 {DELAY*1.3}9E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VDD},{VSS})}}RINT2 YINT3 Y 1 CINT2 Y 0 1n.ENDS BUF_DELAY_BASIC_GEN*$@.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 5E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} &"+ V(C) > {VTHRESH},{VDD},{VSS})}}RINT YINT Y 1 CINT Y 0 1n.ENDS AND3_BASIC_GEN*$.SUBCKT CESR IN OUT$+ PARAMs: C=100u ESR=0.01 X=2 IC=0C IN 1 {C*X} IC={IC}RESR 1 OUT {ESR/X} .ENDS CESR*$.SUBCKT LDCR IN OUT+ PARAMs: L=1u DCR=0.01 IC=0L IN 1 {L} IC={IC}RDCR 1 OUT {DCR} .ENDS LDCR*$FBNC_0NC_1ENABLEBIASCBOOTDAPNC_2NC_7PGND_0PGND_1NC_6NC_3NC_4NC_5AGNDSS_TRKSW_0SW_1RTPGND_2PGND_3PGOODSW_2VIN_0VIN_1VIN_2VCCSW_3SW_4SYNC BC1T_0F3FF28020201213142018CP_CYL300_D700_L1400 (C) M7܉>@eAY@? BhL1T_0F3FF86020201213142031L_CYL200_D350 (L)”/>@Y@$@ BR1T_0F3FFE4020201213142138R_AX600_W200 (R)n燁?@?Y@ BPR2T_0F40042020201213142325R_AX600_W200 (R)j@@?Y@ BPR3T_0F400A0020201213142421R_AX600_W200 (R)Y@@?Y@ BPPR4T_0F400FE020201213142451R_AX600_W200 (R)j@@?Y@ BPR5T_0F4015C020201213142454R_AX600_W200 (R)@@?Y@ B(P C2T_0F401BA020201213142720CP_CYL300_D700_L1400 (C) !s0=@eAY@? BC3T_0F40276020201213142902CP_CYL300_D700_L1400 (C) :0yE>@eAY@? BC4T_0F40390020201213143736CP_CYL300_D700_L1400 (C) }9J?@eAY@? BXR6T_0F403EE020201213143744R_AX600_W200 (R)N ^E?@?Y@ B( R7T_0F404AA020201213143931R_AX600_W200 (R)?@?Y@BPVG1T_0F40566020201213144239 Sgen (VG)(@Mb@??Mb@?ư>ư>ư>,C6? BR8T_0F40622020201213144628R_AX600_W200 (R)j@@?Y@ B0R9T_0F406DE020201213144737R_AX600_W200 (R)6@@?Y@ BC5T_0F4079A020201213144913CP_CYL300_D700_L1400 (C) avt>@eAY@? B`R10T_0F408B4020201213145145R_AX600_W200 (R),C6?@?Y@ BC6T_0F40912020201213145228CP_CYL300_D700_L1400 (C) (FTv>@eAY@? B8R11T_0F40A8A020201213145341R_AX600_W200 (R)@@?Y@ BxR12T_0F40AE8020201213145357R_AX600_W200 (R)jA@?Y@Br(VOUTT_0A5D75F020201213153925 NOPCB (VF)BqPVINT_0A5D879020201213154134 NOPCB (VF)BpXSWT_0A5D8D7020201213154256 NOPCB (VF)BnxVCCT_0F40680020201213144649 NOPCB (J)Bn@VCCT_0F40856020201213145103 NOPCB (J)BoPVOUTT_0A5D7BD020201213153956 NOPCB (J)BnVINT_0A5D81B020201213154044 NOPCB (J)BfPT_0F40218020201213142757 NOPCB (GND)BfT_0F402D4020201213143618 NOPCB (GND)Bf00T_0F40332020201213143627 NOPCB (GND)BfT_0F4044C020201213143810 NOPCB (GND)Bf0T_0F405C4020201213144518 NOPCB (GND)Bf0T_0F4073C020201213144800 NOPCB (GND)BfT_0F407F8020201213144938 NOPCB (GND)BfP(T_0F409CE020201213145241 NOPCB (GND)Bf( T_0F40B46020201213145443 NOPCB (GND)8? ]@"MbP??ư>'dd?Y@[dddd$@?.A.A.AeAMbP?@@?{Gz?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+=:0yU>KH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname