OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 7.0.80.134 SFB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved. $Circuit$L\i?[VOUT]miny1=0maxy1=2 divsy1=1 scaley1=0c!*??ƚEl< EMF,@3A8  RpMS Sans SerifMS Sans Serif ^G^^BW|U|l80uA(+^@IA  TYdv%  &%  '%    M\<= ??l(Ȓ=(=Ȓٝrrrlllrrr槧oootttnnnyyyzzzrrrwww櫫򯯯𹹹WSLFdapoim|||GGGʘwp@7B;FAGG촴о񶶶۹뻻𪪪㿿΢اc\HB>9HEghdoqkkmg`a]~}onpvrx{xwvtsumlh}STR~~jhg^\\}|rmo|v{jdipjovttnikRPPKXR60UNipafjdjjp|v{poapto񰨨gb_hcbɅxuqcosƽpck~v˺[Z60PJqxiKOIUVZߋc`phfyxstqn_옛~}jfazorq|l_guy}ru̠¿º=>MOklhnom\·gsnenllzpqopqhɹPQAedZtpkpme{vu~pǹlj`LQ?@|fbg­kދnuaoWrqgqjmX[____tzy|ɶQWFx咕]`Qȑmp`LO@tvj͋vttBBPKialVNX㯱|ӿөڮ먮Ѯǵ醍~ZaT뵼˰[XONu䟝sqqWUUdba<5`Zxoyǽxnzxqvmmm؃ԛwvB@{ԷՎcd`FGC[ZVSQPVTSywvy?6񽷸wpsxqvyrwtmpjdixrCA|onٱigfy.2'23*873ecbfcez|THSHǿsnLI켹|zzommnll25&24(67.da]kejkcjd\cĥG:~qQI|wݤfc^lhgz|p$'"67-IFBGBC-&+F=Gxjakj_gkagshkeXTG誯yQIusk[XTokjqtelm]wwiutjTQL8433,/7/6||vkuG;}fQVC;,4*3-SP}YP]T^[VURN|xwźtspk52.:45-&)|t{cWcnfp^Uλĺƻǿl]7'J@kd݁zwr:6EA锐⸹}u`[Xuqp|xs+'"740:65{t{^Z_ڻuomjHO>DFHҤ|{mywl{{vs½ÿĵȇ~~vywoVRQmkj㣟Ӽ䦱Τ鞟ץڄ€Ҽ៫ͥ琊ِٗpzRV98yZXK>C>`k56>;os3298hg101199VWqsim48tz\e9BDMrsC;9,;-:.;5}~~I]$7<$ KD64*5;LAP8E?K^iʻs~9@>@/2,/6868fgefSVSWpq}>;D>7/WR̰ηݧpqaacPr}ƿǽʾwy}჎z65>ľ82LH( C?78:8ik65AA23/2u{擘X`+3:?oqchAH9A\a0/QMᕍzrIAC@uws4?{@L?JT]:?;9=9MHut-(DC`jϫjyBNGR,7kkw|QX_b]_cbhfUT|}ljJKVWQS?J~yʜ捇ف|ќ|tFJ>rvjjncW]Rgna˾um|wx_kWECC|ZW:8YZſ¼RS-36:FK,6qv%)59yt8=-;1@CJqqXU45BFqv>9>;z=4A;:><=qr%'EE9>[`FG+.hmGPLYC@tvnn??XVWX6=bm$!}VYPY\S}z{wyzvcfdqvu킋¶ƶ~slzykihtrqö*7',6)TYPsplxzqahȺst76=@MP;=89<9A>SR8=(7Xc=I%8gp -+7:@8HBRCGys`Z7:@DXYC3hicbTUTSFGFNR`C?`b\QSM˾μ¼w{ygttrqRPOCA@ecbqonsqp$EOCsxonkg}uvwio<>EF67FNGOEOEM69BJ%;/B'>_q$;%;MQ!)8׌{@F96wn_[9>BH>B=8NMF@>:dhTb.1ACz)74E $DIeoÒzDJLP,!v~]_CF\YIM7BTd#")*&efdccc{z|䰴ƺĸø¼ʾ~qwigfFDC865MKJpnmywvgedIGF<:9NLK~ɽr~rENDV]Vfeawqrx{NR<=LMIM93yY[6A?KIQ;8GEB>23iqUf%*BBjv%11@[_-0NSqs>CENɾG=ce;<埧┕Ҩⴠ믡?@HQ5BM`հݢߩP\􅆂DECMMMdceedfa`dsrtżôļɬ{twwkSSMLJIJHG][ZusrrpoXVUECBRPOTRQNLKMKJgedþ߈Z`[WXVwsrxysy./EF@F.2Zn-=*@P_|-G%@A?74Ze2F5Her55IF=<.2p,3HE__AA7C41s՜왭=HH\htB4M9?;EP퀀>=?~\X^¶ҿz[\R762PNMecbpnmljiQONECBTRQecbca`[YXOMLLJI`^]psqwutvqp~yx>@25,3;<,9,6Eʡſdo#9'1ETQPWRJK.6):Wd|}%+69yvfPF?:ZUT]5C5BEKNR=KWp]lO]̗jhhijh_]\?=<@hjGR?RtᒘkjDG@G`nzUY5+~`RIDZYR]5C58WRGDMNFHde]TVLLDWQTPOQVTrp]aCF@D~:/s{dcIOUU<6AOBY*3JQ뫩tusnrm`^]RPO][Zca`\ZYca`^\[YWVXVU[YXa_^ecbied~zżIU2920:AQJQD8/HJao+;.`c).I?ǺD7~~AC<8@5G3zy|U4O)N?ͳî:?|PXМ|zyigfwutJNADʖ؎و|̧٩ޚʿݽŪ칱y(4bl屯~|{䵸V[36zL[5DƜquDIUXCNAKzԥRT|Z^GF`tsվęǼ۵Ĵyxzʬú֣ɭ闗议ґ׎ܳ~~~늊ǫ򴴴騨ۥ񯯯͝תŠWVXԵݏ॥ѿ}}}ɉ򯯯vvvqqq}}}əؒtttzzzzzzɻwwwᳲ򔛞ȯígggppp[[[ޫ~~~ܖ{{{~~~ʊ퍍񄄄ʅ瘘㑑쩩齽¸ҏպϙ°𻻻lllᘘ焄rrr̕}}}ԍԙȁ|||~~~ӷÅQPRňΗ眣蕛܏ϊt|Ybu}߫⌌龾⻻qqq＼배⥦֋ɩ6)5&<.?2?4>6>8?;|xvȮįǙǼͣ{{{¨񚖹undmbujvmys”ҷ穦֤ڭ啕𔏌񫭧걱󻻻¼ƽ⿿󶷵媫ʽè% % % VER=1.0Font0=Verdana,14Font1=Verdana,14,BRect0=2,0,0,85,22Rect1=1,0,0,85,10Rect2=1,0,10,10,17Rect3=1,10,10,75,17Rect4=1,75,10,85,17Rect5=1,0,17,50,22Rect6=1,50,17,85,22Text0=0,2,2,TitleText1=0,2,11,SizeText2=0,2,18,DateText3=0,12,11,Document No.Text4=0,77,11,RevText5=0,52,18,SheetText6=0,70,18,ofField0=1,T,11,2,80Field1=1,T,11,5,80Field2=1,S,4,13,5Field3=1,T,14,13,40Field4=1,R,78,13,6Field5=1,D,12,18,30Field6=1,P,64,18,3Field7=1,A,77,18,34F0=Low Voltage Adjustable Precision Shunt Regulator,F3=SLVS139T - July 1996 - Revised June 2007F4=1.00F5=12/28/2009F6=1F7=1>@ Times New Roman  NOTES:41. The PSpice macromodel for TLV431 is unencrypted.12. The reference voltage for this part is 1.24V.93. This testbench is used to run the Transient analysis.C4. Click Analysis ---> Transient... --> OK to run the simulation. H5. The circuit above is the same as Figure 1 in the datasheet SLVS139T.)6. In this Circuit, Vout = Vref = 1.24V.Symbol????333333??1@1 Times New RomanTLV431 Transient AnalysisSymbol????333333??%8@88@!88(88(%8Px8P8x!@0@@0@%@0@@0!!!((!@@%!!!00!@h@h!xxxx!xxD98( V10391992C20091228133009 JP100 (V)@98#V20402B12020091228133020 JP100 (VG)?@V 9hR10402B95C20091228133024R_AX300_W100 (R)@@@?Y@ 9@R20392B18C20091228133028R_AX300_W100 (R)@@?Y@9f0VOUT:204230798200912281341569e@ VIN:10349364420091228134212:9:U1057169E820091228135845 TLV431TLV431[C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV431\Active_Work\TINA\TLV431_TINA\TLV431.CIRSCK#TLV431Label  PP(d*Fdbk 1997 Design @d*A  @d*K@  @h eddeddeddeddeddeddedd=@=@?*$ * TLV431N*****************************************************************************N* (C) Copyright 2009 Texas Instruments Incorporated. All rights reserved. **N*****************************************************************************N** Thismodelis designed as an aid for customers of Texas Instruments. **N**TI and itslicensors and suppliers makeno warranties, either expressed **N** or implied, with respect to thismodel, including thewarranties of **N** merchantability or fitness fora particular purpose. The model is **N** provided solely on an "as is" basis. The entirerisk as to its quality **Q** and performance is with the customer ** N******************************************************************************B* This model was developed for Texas Instruments Incorporated by:* AEi Systems, LLC&* 5933 W. Century Blvd., Suite 1100#* Los Angeles, California 90045*Z* This model is subject to change without notice. Neither Texas Instruments Incorporated :* nor AEi Systems is responsible for updating this model.T* For more information regarding modeling services, model libraries and simulation Y* products, please call AEi Systems at (310) 216-1144, or contact AEi Systems by email: I* info@AENG.com. Or visit AEi Systems on the web at http://www.AENG.com.*N******************************************************************************B** Released by: Analog eLab Design Center, Texas Instruments Inc.* Part: TLV431* Date: 12/28/2009* Simulator: TINA-TI #* Simulator Version: 7.0.80.134 SF7* Datasheet: SLVS139T - July 1996 - Revised June 2007 ** Model Version: Final 1.00*N****************************************************************************** * Updates:* * Final 1.00* Release to Web.*N*****************************************************************************.SUBCKT TLV431 A K FdbkV_V2 N59715 A 1.24)G_G4 K A TABLE { V(STAGE2, A) } $+ ( (-10,0)(0,0)(15m,15m)(10,16m) )R_R1 A STAGE1 1 R_R2 A STAGE2 1 C_C2 A STAGE1 159e-6 C_C3 A STAGE2 80n $G_G1 A STAGE1 Fdbk N59715 4(X_D1 A STAGE1 DC_1mV_1A_1V_1nA!G_G3 A STAGE2 STAGE1 A 1-X_D2 STAGE1 N59689 DC_1mV_1A_1V_1nA#X_D3 A K DC_1mV_1A_1V_1nAV_V1 N59689 A 15m .ENDS TLV431*$.subckt DC_1mV_1A_1V_1nA A CCG1 A C TABLE { V(A, C) } ( (-1,-1n)(0,0)(1m,1) (2m,10) (3m,1000) ).ends DC_1mV_1A_1V_1nA *$FdbkAK9bx0402AC6820091228133013 NOPCB (GND)-?@1^@ư>?&dd?Y@[dddd$@?.A.A.AeAMbP?@@?MbP?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .> ;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@#B ;ư>?.AMbP???Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%IT