OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$w?;T_036351F020200601164709;xxT_035C03A020200601164709;T_05EFA26020200601164709;xxT_05F0F08020200601164709;8888T_0635B19020200601164709;8`88`8T_0634E0F020200601164709;PxPPxPT_06314F3020200601164709;xxT_0630A92020200601164709;hhT_062E05E020200601164709;hhT_062C998020200601164709;T_062CC68020200601164709;PPPPT_062CC2C020200601164709;T_0627E67020200601164744;T_06272AD020200601164750;T_0626640020200601164756;T_062423A020200601164806DB V2T_116BD06020200601163726Battery_9V_V (V)@BqVF1T_116BDC2020200601163748 NOPCB (VF)BqVF2T_116BE20020200601163752 NOPCB (VF)DBP V1T_0398ABE020200601164536Battery_9V_V (V)BVG1T_0398CF2020200601164643 Sgen (VG)@?wAVDB V3T_0398EC8020200601164709Battery_9V_V (V)@:B[ U1T_0D0C970020200602112456  TLV3202_Q1 TLV3202_Q1VC:\Users\a0227287\AppData\Local\Temp\DesignSoft\{Tina9-TI-01072020-103954}\TLV3202_Q1SCK# TLV3202_Q1LabelDD#`0d*1IN-=V(2)),V(VSS  @d*1IN+Dq @d*2IN+  @d*1OUT_EN)>V(VMID) ` @d*2OUT+V(VSS_B))/2 ` @d*2IN-V(2)-1M),V(V ( @d*VCC-D 0 VALUE =  0 @d*GND 00 @g% TLV3202_Q1Arial@'333333?eAddeidde@hdd@!w8z@@!w8z@* source TLV3202_Q1 N*****************************************************************************J* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedH** or implied, with respect to this model, including the warranties of F** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality)** and performance is with the customer.N******************************************************************************D* This model is subject to change without notice. Texas Instruments:* Incorporated is not responsible for updating this model*N******************************************************************************'** Released by: Texas Instruments Inc.* Part: TLV3202-Q1* Date: 06/02/2020* Model Type: All In One* Simulator: PSPICE !* Simulator Version: 16.6.0.p001* EVM Order Number: N/A * EVM Users Guide: N/A !* Datasheet: SBOS856A - Dec 2017** Model Version: 1.0*N****************************************************************************** * Updates:*'* Version 1.0 : Release to Web *N***************************************************************************** * Notes:)* The following parameters are modeled: ,* Iq, tpd, trise/fall, Vcm, Vs, Vhys, Ibiasy* If either input goes beyond the absolute maximum range, the output will float to mid supply for the respsective output^* If the supply goes beyond the absolute maximum range, both outputs will float to mid supply`* If both inputs go beyond the recommended operating range, the output will float to mid supplye* If one input goes beyond the recommended operating range, the output will reflect the input state N*****************************************************************************;.SUBCKT TLV3202_Q1 1IN+ 1IN- 1Out 2IN+ 2IN- 2Out GND Vcc 8X_U1 1IN+ 1IN- 1OUT 2IN+ 2IN- 2OUT GND VCC SCHEMATIC1 .ENDS ;.SUBCKT SCHEMATIC1 1IN+ 1IN- 1OUT 2IN+ 2IN- 2OUT GND Vcc 3X_U38 1IN+_B 1IN-_B ABSMAX1_EN VDD_B VSS_B VinEn X_U46 N701319 N701325 Delay =X_U43 ABSMAX2_EN CM2_EN VIN2_EN VDD_B VSS_B ANDGATEX_U34 N690186 N690192 Delay 3X_U42 2IN+_B 2IN-_B ABSMAX2_EN VDD_B VSS_B VinEn V_1_1_2m HYS 0 2.4mI_I2 1IN+ 0 DC 1e-12 I_I4 2IN+ 0 DC 1e-12 CX_U33 SUPPLY_EN VIN1_EN VDD_B VSS_B N690192 1OUT OUTPUT_EN'X_U36 SUPPLY_EN VDD_B VSS_B SupplyEn /X_U41 2IN+_B 2IN-_B CM2_EN VDD_B VSS_B VinCM I_I1 VCC 0 DC 40e-6 I_I3 1IN- 0 DC 1e-12 4X_U39 1IN+ 1IN- 1IN+_B 1IN-_B SUPPLY_BUFFER4X_U40 2IN+ 2IN- 2IN+_B 2IN-_B SUPPLY_BUFFERI_I5 2IN- 0 DC 1e-12 @X_U28 1IN+_B 1IN-_B N690186 VDD_B VSS_B HYS hpa_comphys/X_U37 1IN+_B 1IN-_B CM1_EN VDD_B VSS_B VinCM /X_U1 VCC GND VDD_B VSS_B SUPPLY_BUFFER=X_U16 ABSMAX1_EN CM1_EN VIN1_EN VDD_B VSS_B ANDGATECX_U44 SUPPLY_EN VIN2_EN VDD_B VSS_B N701325 2OUT OUTPUT_EN@X_U45 2IN+_B 2IN-_B N701319 VDD_B VSS_B HYS hpa_comphys.ENDS ,.SUBCKT VinCM IN+ IN- INRANGE VDD_B VSS_B 6X_U22 IN- N37445 N37365 VDD_B VSS_B VCC_RANGEV_V7 N37173 VDD_B 0.28X_U23 N36791 N36891 N36881 VDD_B VSS_B ANDGATE8X_U16 N37241 N37365 N37101 VDD_B VSS_B ANDGATEV_V1 N36731 VDD_B 0.2V_V6 N37005 VSS_B -0.25X_U5 N36731 IN+ N36791 VDD_B VSS_B VCC_RANGE6X_U20 IN+ N37005 N36891 VDD_B VSS_B VCC_RANGE7X_U19 N36881 N37101 INRANGE VDD_B VSS_B ORGATE6X_U21 N37173 IN- N37241 VDD_B VSS_B VCC_RANGEV_V4 N37445 VSS_B -0.2.ENDS ".SUBCKT SupplyEn EN VDD_B VSS_B V_V1 N683382 0 7;X_U5 N683382 N683418 N683394 VDD_B VSS_B VCC_RANGEV_V2 N683590 0 -.3 (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS$.SUBCKT Difference 1 2 OUT VDD VSS !EOUT OUT 0 VALUE = { V(1)- V(2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS2 .SUBCKT hpa_comphys INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }aEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH)) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSSeEOUT OUT 0 VALUE = { IF( ((V(1) < (V(VDD)+V(VSS))/2 ) & (V(2) < (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS1.SUBCKT OUTPUT_EN VS_EN IN_EN VDD_B VSS_B IN OUT3EVMID VMID 0 VALUE = { ( V(VDD_B) + V(VSS_B) )/2 }^EOUT OUT 0 VALUE = { IF( ((V(VS_EN)> V(VMID) ) & (V(IN_EN) > (V(VMID) ))), V(IN), V(VMID) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS&.SUBCKT SUPPLY_BUFFER 1 2 VDD_B VSS_B EVDD_NEW VDD_B 0 VALUE = {V(1)} EVSS_NEW VSS_B 0 VALUE = {V(2)} C1 2 0 1e-12.ENDS#.SUBCKT VCC_Range 1 2 OUT VDD VSS BEOUT OUT 0 VALUE = { IF( ( V(1) > V(2) - 1m ), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS1IN-1IN+2IN+1OUT2OUT2IN-VCCGNDBnxVccT_0398FE2020200601164543 NOPCB (J)BnPxGndT_0398B1C020200601164551 NOPCB (J)Bn8`VccT_0398B7A020200601164624 NOPCB (J)Bn8GndT_0398BD8020200601164629 NOPCB (J)BnxIN+T_0398C94020200601164637 NOPCB (J)BnxIN-T_0398DAE020200601164652 NOPCB (J)BnIN+T_0398F26020200601164735 NOPCB (J)BnIN+T_0398F84020200601164747 NOPCB (J)BnIN-T_039915A020200601164753 NOPCB (J)BnIN-T_03991B8020200601164802 NOPCB (J)BfPT_116BB8E020200601163035 NOPCB (GND)BfT_116BD64020200601163732 NOPCB (GND)BfT_0398D50020200601164648 NOPCB (GND)BfT_0398C36020200601164652 NOPCB (GND)8? ]@"MbP??ư>'dd?Y@[dddd$@?.A.A.AeAMbP?@@?I׊>ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname